[PATCH 3/6] clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768

[Alexey Charkov]

Current code needlessly sets the k value to 0 when it is calculated as
-32768, which is a valid value for the RK3588 frac PLL. This results in
the PLL output frequency being higher than requested when the requested
frequency is exactly halfway between two integer-multiplier PLL output
frequencies.

Negative k values can never go below -32768 either, because that case is
handled just above this code, so the check for k > 32767 is redundant.

What remains of the if statement is a hand-rolled two's complement
negation of the result, so write it out as such for clarity, and return
the true S16 type of k as specified in the TRM.

Fixes: 6bfb37e70209 ("clk: rockchip: rk3588: fix up the frac pll calculation")
Signed-off-by: Alexey Charkov <alch...@flipper.net>
---
 drivers/clk/rockchip/clk_pll.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 69d2d182dcb5..c6fbeb71c77a 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -167,11 +167,11 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
        return rate_table;
 }
 
-static u32
+static s16
 rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
 {
        u64 fref, ffrac;
-       u32 k = 0;
+       int k;
 
        fref = fin_hz / p;
        ffrac = fvco - (m * fref);
@@ -181,11 +181,7 @@ rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, 
u64 fvco)
                /*
                 * Round up to avoid overshooting requested rate for negative k
                 */
-               k = DIV64_U64_ROUND_UP(ffrac * 65536, fref);
-               if (k > 32767)
-                       k = 0;
-               else
-                       k = ~k + 1;
+               k = -(int)DIV64_U64_ROUND_UP(ffrac * 65536, fref);
        }
        return k;
 }

-- 
2.53.0