The TRM defines the fractional PLL adjustment coefficient as a signed two's complement number, 16 bits wide, so store it as such to avoid confusion.
Signed-off-by: Alexey Charkov <[email protected]> --- arch/arm/include/asm/arch-rockchip/clock.h | 2 +- drivers/clk/rockchip/clk_pll.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 95b08bfd046f..f9bfdfb8a6a3 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -104,7 +104,7 @@ struct rockchip_pll_rate_table { unsigned int m; unsigned int p; unsigned int s; - unsigned int k; + int k; }; enum rockchip_pll_type { diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 6324c11091af..ebe90b55ea06 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -195,8 +195,9 @@ static struct rockchip_pll_rate_table * rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz) { struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; - u32 p, m, s, k; + u32 p, m, s; u64 fvco; + s16 k; for (s = 0; s <= 6; s++) { fvco = (u64)fout_hz << s; -- 2.53.0
