The best rate handling of rk3588_dclk_vop_set_clk() may unintentionally trigger a divide by zero when V0PLL is tested as parent. Instead, fully skip rate calculation when testing using V0PLL as parent to avoid a divide by zero error.
Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 157a02e011a5..d03ca9c4ac8d 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1165,8 +1165,8 @@ static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv, pll_rate = priv->aupll_hz; break; case DCLK_VOP_SRC_SEL_V0PLL: - pll_rate = 0; - break; + /* Skip V0PLL as parent for best_rate mode */ + continue; default: printf("do not support this vop pll sel\n"); return -EINVAL; -- 2.54.0
