The SPLL rate is set to 702 MHz in SPL. Replace '702 * MHz' with use of the SPLL_HZ constant to enhance readability.
Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_rk3588.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index c48743d8296f..1006102f4cf4 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -777,7 +777,7 @@ static ulong rk3588_mmc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; if (sel == DCLK_DECOM_SEL_SPLL) - prate = 702 * MHz; + prate = SPLL_HZ; else prate = priv->gpll_hz; return DIV_TO_RATE(prate, div); @@ -817,9 +817,9 @@ static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv, } break; case DCLK_DECOM: - if (!(702 * MHz % rate)) { + if (!(SPLL_HZ % rate)) { src_clk = DCLK_DECOM_SEL_SPLL; - div = DIV_ROUND_UP(702 * MHz, rate); + div = DIV_ROUND_UP(SPLL_HZ, rate); } else { src_clk = DCLK_DECOM_SEL_GPLL; div = DIV_ROUND_UP(priv->gpll_hz, rate); @@ -942,7 +942,7 @@ static ulong rk3588_aclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) else if (sel == ACLK_VOP_ROOT_SEL_NPLL) parent = priv->npll_hz; else - parent = 702 * MHz; + parent = SPLL_HZ; return DIV_TO_RATE(parent, div); case ACLK_VOP_LOW_ROOT: con = readl(&cru->clksel_con[110]); -- 2.54.0
