The ACLK_BUS_ROOT is typically using CPLL as parent clock and running at 500 MHz out of reset when CPLL is running at 1.5 GHz.
The parent and rate of ACLK_BUS_ROOT is changed to use GPLL and to run at 237 MHz during clock driver probe. However, the clock rate is hardcoded to be reported as 375 MHz. Change to explicitly use CPLL as parent and set the rate to 375 MHz, to match the reported rate and closer match how the Linux configures the clock. Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_rk3588.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index d03ca9c4ac8d..c48743d8296f 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1921,11 +1921,11 @@ static void rk3588_clk_init(struct rk3588_clk_priv *priv) { int ret, div; - div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz); + div = DIV_ROUND_UP(CPLL_HZ, 375 * MHz); rk_clrsetreg(&priv->cru->clksel_con[38], - ACLK_BUS_ROOT_SEL_MASK | - ACLK_BUS_ROOT_DIV_MASK, - div << ACLK_BUS_ROOT_DIV_SHIFT); + ACLK_BUS_ROOT_SEL_MASK | ACLK_BUS_ROOT_DIV_MASK, + (ACLK_BUS_ROOT_SEL_CPLL << ACLK_BUS_ROOT_SEL_SHIFT) | + (div - 1) << ACLK_BUS_ROOT_DIV_SHIFT); if (priv->cpll_hz != CPLL_HZ) { ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, -- 2.54.0
