The RK3568 clock driver has a few trivial copy-paste mistakes in its clock handling.
Fix the trivial clock configuration errors: - use correct pll_id for GPLL - use correct shift macro for PWM0 div - use correct pll rate for GMAC src clock Signed-off-by: Jonas Karlman <[email protected]> --- drivers/clk/rockchip/clk_rk3568.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index bb49af358e60..940b824103cc 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -77,7 +77,7 @@ static struct rockchip_pll_clock rk3568_pll_clks[] = { RK3568_MODE_CON, 2, 10, 0, NULL), [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24), RK3568_MODE_CON, 4, 10, 0, rk3568_pll_rates), - [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16), + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3568_PLL_CON(16), RK3568_MODE_CON, 6, 10, 0, rk3568_pll_rates), [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32), RK3568_MODE_CON, 10, 10, 0, rk3568_pll_rates), @@ -294,12 +294,12 @@ static ulong rk3568_pwm_set_pmuclk(struct rk3568_pmuclk_priv *priv, CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK, (CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT) | - 0 << CLK_PWM0_SEL_SHIFT); + 0 << CLK_PWM0_DIV_SHIFT); } else { src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); assert(src_clk_div - 1 <= 127); rk_clrsetreg(&pmucru->pmu_clksel_con[6], - CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK, + CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK, (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) | (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); } @@ -1882,7 +1882,7 @@ static ulong rk3568_gmac_src_get_clk(struct rk3568_clk_priv *priv, case CLK_MAC0_2TOP_SEL_25M: return 25 * MHz; case CLK_MAC0_2TOP_SEL_PPLL: - return rk3568_pmu_pll_get_rate(priv, HPLL); + return rk3568_pmu_pll_get_rate(priv, PPLL); default: return -ENOENT; } -- 2.54.0
