Convert to use the rockchip_sysreset_bind() helper to bind the rockchip_sysreset driver. Also add and use a CRU base address constant based on the clock-controller address used in the SoC device tree.
Signed-off-by: Jonas Karlman <[email protected]> --- .../arm/include/asm/arch-rockchip/cru_rk322x.h | 2 ++ drivers/clk/rockchip/clk_rk322x.c | 18 +++++------------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index ee12fa831f28..707cc2f4b9fc 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -64,6 +64,8 @@ struct pll_div { u32 frac; }; +#define RK322X_CRU_BASE 0x110e0000 + enum { /* PLLCON0*/ PLL_BP_SHIFT = 15, diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 9b71fd863bad..680e4faf31ed 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -495,22 +495,14 @@ static int rk322x_clk_probe(struct udevice *dev) static int rk322x_clk_bind(struct udevice *dev) { int ret; - struct udevice *sys_child; - struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", - &sys_child); - if (ret) { + ret = rockchip_sysreset_bind(dev, RK322X_CRU_BASE, + offsetof(struct rk322x_cru, cru_glb_rst_st), + offsetof(struct rk322x_cru, cru_glb_srst_fst_value), + offsetof(struct rk322x_cru, cru_glb_srst_snd_value)); + if (ret) debug("Warning: No sysreset driver: ret=%d\n", ret); - } else { - priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk322x_cru, - cru_glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk322x_cru, - cru_glb_srst_snd_value); - dev_set_priv(sys_child, priv); - } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk322x_cru, cru_softrst_con[0]); -- 2.54.0
