Convert to use the rockchip_sysreset_bind() helper to bind the rockchip_sysreset driver. Also add and use a CRU base address constant based on the clock-controller address used in the SoC device tree.
Signed-off-by: Jonas Karlman <[email protected]> --- arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 2 ++ drivers/clk/rockchip/clk_rk3188.c | 17 ++++------------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h index eec4815bbc06..7f019167a784 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -51,6 +51,8 @@ struct rk3188_cru { }; check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); +#define RK3188_CRU_BASE 0x20000000 + /* CRU_CLKSEL0_CON */ enum { /* a9_core_div: core = core_src / (a9_core_div + 1) */ diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index d8b03e1d7ab3..0e7d1ccb410c 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -577,22 +577,13 @@ static int rk3188_clk_probe(struct udevice *dev) static int rk3188_clk_bind(struct udevice *dev) { int ret; - struct udevice *sys_child; - struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", - &sys_child); - if (ret) { + ret = rockchip_sysreset_bind(dev, RK3188_CRU_BASE, 0, + offsetof(struct rk3188_cru, cru_glb_srst_fst_value), + offsetof(struct rk3188_cru, cru_glb_srst_snd_value)); + if (ret) debug("Warning: No sysreset driver: ret=%d\n", ret); - } else { - priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3188_cru, - cru_glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3188_cru, - cru_glb_srst_snd_value); - dev_set_priv(sys_child, priv); - } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3188_cru, cru_softrst_con[0]); -- 2.54.0
