From: Ye Li <[email protected]>
This patch series enables icache and dcache at the earliest possible
point in the SPL and U-Boot boot flow for iMX95, iMX94, and iMX952
platforms, significantly reducing boot time.
On iMX9x platforms using SCMI, the DDR size is not known until the
System Manager (SM) is queried via SCMI during DM init. This makes
it impossible to set up a full MMU table before DM init completes.
To work around this, the early MMU table maps the entire DDR address
space as device memory (preventing speculative prefetch into unknown
regions), while mapping only the low 64MB of SDRAM as normal memory
to cover SPL, U-Boot, early malloc, and the stack. Once DM init completes
and the effective DDR size is known, the MMU table is updated to
reflect the actual effective memory.
For SPL, the secure DDR region (CFG_SYS_SECURE_SDRAM_BASE/SIZE) must
be defined by the board to provide a location for the SPL MMU page
table and cover the destination of loaded images. The first 2MB of this
region is used by default for MMU table. Boards must also move arch_cpu_init()
before spl_early_init() to activate caches before DM init begins, since
the main target is saving the time in DTB parsing in DM init.
Measured on iMX95 EVK booting from SD card:
SPL boot time saved: ~87 ms
U-Boot boot time saved: ~402 ms
Ye Li (4):
imx9: scmi: Move WDOG and GPIO init out of arch_cpu_init
imx9: scmi: Support early caches enable in SPL and u-boot
spl_imx_container: Fix verify image after SPL dcache enabled
nxp: imx9{5,4,52} evk/frdm : Enable caches in SPL
arch/arm/mach-imx/imx9/scmi/soc.c | 156 +++++++++++++++++++++++++++++-
board/nxp/imx94_evk/spl.c | 4 +-
board/nxp/imx952_evk/spl.c | 4 +-
board/nxp/imx95_evk/spl.c | 4 +-
board/nxp/imx95_frdm/spl.c | 4 +-
common/spl/spl_imx_container.c | 2 +
include/configs/imx94_evk.h | 3 +
include/configs/imx952_evk.h | 2 +-
include/configs/imx95_evk.h | 3 +
include/configs/imx95_frdm.h | 3 +
10 files changed, 173 insertions(+), 12 deletions(-)
--
2.50.1
