Hello Ye, On Tue, Sep 22, 2026 at 05:32:01PM +0800, Ye Li wrote: > On 9/22/2026 1:38 PM, Francesco Dolcini wrote: > > On Tue, Sep 22, 2026 at 10:24:02AM +0800, [email protected] wrote: > > > From: Ye Li <[email protected]> > > > > > > This patch series enables icache and dcache at the earliest possible > > > point in the SPL and U-Boot boot flow for iMX95, iMX94, and iMX952 > > > platforms, significantly reducing boot time. > > > > > > > You did not update the Toradex boards (that are the only iMX95 boards > > not from NXP currently present in U-Boot). > > > > Is something that should be done? > > Yes, I only update NXP boards. By default, the u-boot early caches are > enabled in the patch set, no change needed for Toradex board. To enable > caches in SPL, Toradex boards need to update codes like patch #4 to define > the CFG_SYS_SECURE_SDRAM_BASE/SIZE and move arch_cpu_init().
Is something that you can do and make sense to be done as part of this series? > > > On iMX9x platforms using SCMI, the DDR size is not known until the > > > System Manager (SM) is queried via SCMI during DM init. > > > > Emanuele: is this the same also for Toradex boards? I think for us is > > different. Any significant implication because of that? > > > The default board_phy_sdram_size gets the DDR size from SM. If Toradex > boards don't override it, you are using same way. This allow single u-boot > image working for boards with different DDR size. We have the same binary images using the same U-Boot/OEI and SM and everything for board with different memory. But to have this we had to deviate from what NXP does. Francesco
