Hello Ye, On Tue, Sep 22, 2026 at 10:24:02AM +0800, [email protected] wrote: > From: Ye Li <[email protected]> > > This patch series enables icache and dcache at the earliest possible > point in the SPL and U-Boot boot flow for iMX95, iMX94, and iMX952 > platforms, significantly reducing boot time. >
You did not update the Toradex boards (that are the only iMX95 boards not from NXP currently present in U-Boot). Is something that should be done? > On iMX9x platforms using SCMI, the DDR size is not known until the > System Manager (SM) is queried via SCMI during DM init. Emanuele: is this the same also for Toradex boards? I think for us is different. Any significant implication because of that? Francesco
