The system timer register might be secure and not allow uboot to access. BL31 is responsible for the configuration.
Signed-off-by: Stanley Chu <[email protected]> Signed-off-by: Jim Liu <[email protected]> --- arch/arm/mach-npcm/npcm8xx/cpu.c | 40 -------------------------------- 1 file changed, 40 deletions(-) diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index a1fb400b264..4deffb7b845 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -4,34 +4,11 @@ */ #include <dm.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/system.h> #include <asm/arch/gcr.h> #include <asm/armv8/mmu.h> -#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000 -#define SC_CNTCR_ENABLE BIT(0) -#define SC_CNTCR_HDBG BIT(1) -#define SC_CNTCR_FREQ0 BIT(8) -#define SC_CNTCR_FREQ1 BIT(9) - -/* System Counter register map */ -struct sctr_regs { - u32 cntcr; - u32 cntsr; - u32 cntcv1; - u32 cntcv2; - u32 resv1[4]; - u32 cntfid0; - u32 cntfid1; - u32 cntfid2; - u32 resv2[1001]; - u32 counterid[1]; -}; - -DECLARE_GLOBAL_DATA_PTR; - int print_cpuinfo(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; @@ -125,20 +102,3 @@ static struct mm_region npcm_mem_map[] = { }; struct mm_region *mem_map = npcm_mem_map; - -int timer_init(void) -{ - struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; - u32 cntfrq_el0; - - /* Enable system counter */ - __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory"); - writel(cntfrq_el0, &sctr->cntfid0); - clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, - SC_CNTCR_ENABLE | SC_CNTCR_HDBG); - - gd->arch.tbl = 0; - gd->arch.tbu = 0; - - return 0; -} -- 2.34.1
