The QCS8300 clock driver has no SDCC1 clocks, so the eMMC controller on QCS8300 boards fails to probe. Add the SDCC1 AHB and APPS clock gates and the APPS clock rate, from CXO and GPLL0_EVEN up to 100 MHz.
Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Tyler Baker <[email protected]> --- drivers/clk/qcom/clock-qcs8300.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c index cd8aecdf78..ac5b28ae34 100644 --- a/drivers/clk/qcom/clock-qcs8300.c +++ b/drivers/clk/qcom/clock-qcs8300.c @@ -16,10 +16,20 @@ #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 +#define SDCC1_APPS_CLK_CMD_RCGR 0x20014 + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; static ulong qcs8300_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", @@ -36,6 +46,11 @@ static ulong qcs8300_set_rate(struct clk *clk, ulong rate) 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); clk_rcg_set_rate(priv->base, 0xf064, 0, 0); return rate; + case GCC_SDCC1_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return 0; } @@ -53,6 +68,8 @@ static const struct gate_clk qcs8300_clks[] = { GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0)), GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0)), GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0)), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0)), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0)), }; static int qcs8300_enable(struct clk *clk) -- 2.47.3
