On Fri, Sep 25, 2026 at 8:38 AM Casey Connolly <[email protected]> wrote: > > Hi Tyler/Claude, > > On 9/25/26 01:38, Tyler Baker wrote: > > The QCS8300 clock driver has no QUPv3 clocks, so every QUP serial > > engine in the device tree asks for a clock the driver does not know: > > > > gcc@0x100000: unknown clock ID 109! > > gcc@0x100000: unknown clock ID 117! > > gcc@0x100000: unknown clock ID 121! > > useless context > > > > > Add the QUPv3 wrapper 0, 1 and 3 serial engine, core and AHB clocks. > > They are branch vote clocks: each is enabled through its bit in the > > APCS clock branch vote registers and polled on its branch status > > register, as the Linux QCS8300 GCC driver describes them. Rates are > > left as the boot firmware set them, as for SA8775P. > > more useless context which doesn't belong here, this is not what a good > commit message looks like. > > I'll let you respin this series before i take a look at the other > patches, using LLM slop commit messages like this is frankly just > disrespectful, nevermind confusing and polluting to the quality of the > codebase. NAK
Ack, apologies, I'll fix this up in the next series.
