Re: [PATCH 2/7] clk: qcom: qcs8300: add QUPv3 clocks

[Casey Connolly]

Hi Tyler/Claude,

On 9/25/26 01:38, Tyler Baker wrote:
The QCS8300 clock driver has no QUPv3 clocks, so every QUP serial
engine in the device tree asks for a clock the driver does not know:
   gcc@0x100000: unknown clock ID 109!
   gcc@0x100000: unknown clock ID 117!
   gcc@0x100000: unknown clock ID 121!

useless context


Add the QUPv3 wrapper 0, 1 and 3 serial engine, core and AHB clocks.
They are branch vote clocks: each is enabled through its bit in the
APCS clock branch vote registers and polled on its branch status
register, as the Linux QCS8300 GCC driver describes them. Rates are
left as the boot firmware set them, as for SA8775P.

more useless context which doesn't belong here, this is not what a good 
commit message looks like.

I'll let you respin this series before i take a look at the other 
patches, using LLM slop commit messages like this is frankly just 
disrespectful, nevermind confusing and polluting to the quality of the 
codebase. NAK


Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Tyler Baker <tyler.ba...@oss.qualcomm.com>
---
  drivers/clk/qcom/clock-qcs8300.c | 60 ++++++++++++++++++++++++++++++++++++++++
  1 file changed, 60 insertions(+)

diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c
index ac5b28ae34..361b74d709 100644
--- a/drivers/clk/qcom/clock-qcs8300.c
+++ b/drivers/clk/qcom/clock-qcs8300.c
@@ -70,6 +70,66 @@ static const struct gate_clk qcs8300_clks[] = {
        GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0)),
        GATE_CLK(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0)),
        GATE_CLK(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0)),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x4b008, BIT(9),
+                       0x23018),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_CLK, 0x4b008, BIT(8),
+                       0x2300c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, BIT(10),
+                       0x2314c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S1_CLK, 0x4b008, BIT(11),
+                       0x23280),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S2_CLK, 0x4b008, BIT(12),
+                       0x233b4),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S3_CLK, 0x4b008, BIT(13),
+                       0x234e8),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S4_CLK, 0x4b008, BIT(14),
+                       0x2361c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S5_CLK, 0x4b008, BIT(15),
+                       0x23750),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S6_CLK, 0x4b008, BIT(16),
+                       0x23884),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S7_CLK, 0x4b008, BIT(17),
+                       0x239b8),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x4b008, BIT(18),
+                       0x24018),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_CLK, 0x4b008, BIT(19),
+                       0x2400c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S0_CLK, 0x4b008, BIT(22),
+                       0x2414c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S1_CLK, 0x4b008, BIT(23),
+                       0x24280),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S2_CLK, 0x4b008, BIT(24),
+                       0x243b4),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S3_CLK, 0x4b008, BIT(25),
+                       0x244e8),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S4_CLK, 0x4b008, BIT(26),
+                       0x2461c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S5_CLK, 0x4b008, BIT(27),
+                       0x24750),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S6_CLK, 0x4b018, BIT(27),
+                       0x24884),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S7_CLK, 0x4b018, BIT(28),
+                       0x249b8),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_2X_CLK, 0x4b000, BIT(24),
+                       0xc4018),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_CLK, 0x4b000, BIT(23),
+                       0xc400c),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP3_QSPI_CLK, 0x4b000, BIT(26),
+                       0xc4284),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, BIT(25),
+                       0xc4150),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x4b008, BIT(6),
+                       0x23004),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x4b008, BIT(7),
+                       0x23008),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x4b008, BIT(20),
+                       0x24004),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x4b008, BIT(21),
+                       0x24008),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_M_AHB_CLK, 0x4b000, BIT(27),
+                       0xc4004),
+       GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_S_AHB_CLK, 0x4b000, BIT(20),
+                       0xc4008),
  };
  
  static int qcs8300_enable(struct clk *clk)