Add the eDP transmitter, its PHY and the DVO output stage that feeds it, along with the DP_TX and EDP_TX_DORMANT power domains the transmitter sits in, which were missing from the SPM node. Label the apmixedsys clock controller so that the DVO node can name the PLL it retunes for the pixel clock.
The transmitter's domain is nested below DP_TX, which is itself below the display domain, as in the in-flight "arm64: dts: mediatek: Add mt8189 evaluation board dts" series. U-Boot derives the power-on order from this nesting alone, so describing it flat would leave DP_TX unpowered when the transmitter is brought up. The PHY is described as a node of its own, referenced by the transmitter through "phys", the way the in-flight "PHY: MediaTek DP PHY refactor and MT8196 eDP" series describes the MT8196 eDP PHY. The PHY holds both its analog and its digital register banks, and the transmitter's registers start right after where the PHY used to sit in older SoCs, so the transmitter node starts at 0x11b72000. All three new nodes are disabled: a board enables them only if it routes the display pipeline to eDP rather than DSI. Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8189.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index 22c1c7761f1..0f659908f32 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -179,7 +179,21 @@ <&mmsys CLK_MM_SMI_LARB>; clock-names = "disp", "ss-disp"; mediatek,infracfg = <&infracfg_ao>; - #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8189_POWER_DOMAIN_DP_TX { + reg = <MT8189_POWER_DOMAIN_DP_TX>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8189_POWER_DOMAIN_EDP_TX_DORMANT { + reg = <MT8189_POWER_DOMAIN_EDP_TX_DORMANT>; + #power-domain-cells = <0>; + }; + }; }; }; @@ -399,7 +413,7 @@ reg = <0 0x10001000 0 0x1000>; }; - clock-controller@1000c000 { + apmixedsys_clk: clock-controller@1000c000 { compatible = "mediatek,mt8189-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; @@ -816,6 +830,24 @@ status = "disabled"; }; + edp_tx: edp-tx@11b72000 { + compatible = "mediatek,mt8189-edp-tx"; + reg = <0 0x11b72000 0 0x12000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_EDP_TX_DORMANT>; + phys = <&edp_phy>; + max-linkrate-mhz = <5400>; + status = "disabled"; + }; + + edp_phy: phy@11e10000 { + compatible = "mediatek,mt8189-edp-phy"; + reg = <0 0x11e10000 0 0x1500>; + power-domains = <&spm MT8189_POWER_DOMAIN_EDP_TX_DORMANT>; + #phy-cells = <0>; + status = "disabled"; + }; + mutex0: mutex@14001000 { compatible = "mediatek,mt8189-disp-mutex"; reg = <0 0x14001000 0 0x1000>; @@ -879,6 +911,18 @@ status = "disabled"; }; + disp_dvo0: dvo@14017000 { + compatible = "mediatek,mt8189-edp-dvo"; + reg = <0 0x14017000 0 0x1000>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8189_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MMSYS_1_DISP_DVO>, + <&mmsys CLK_MMSYS_0_DISP_DVO>, + <&apmixedsys_clk CLK_APMIXED_TVDPLL2>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + smi_larb0: larb@1401c000 { compatible = "mediatek,mt8189-smi-larb"; reg = <0 0x1401c000 0 0x1000>; -- 2.53.0
