> Add a video uclass driver for the embedded DisplayPort transmitter found > on MediaTek SoCs such as the MT8189. > > The register programming, the AUX transport and the link training > sequence are based on the Linux driver drivers/gpu/drm/mediatek/mtk_dp.c, > reduced to what a bootloader needs: one panel, one mode, no hot plug > handling and no audio. The PHY is a device of its own, driven through > the PHY uclass, as the in-flight "drm: MediaTek DisplayPort cleanups and > MT8196 eDP" series does in Linux. Register offsets are therefore relative > to the transmitter itself, without the 0x2000 the PHY used to occupy > ahead of it. > > The driver owns the whole output path: it brings up the vdosys0 front > end (OVL, RDMA, SMI and the display mutex), routes it to the DVO output > stage, and drives the transmitter and its PHY. > > On probe the driver powers the panel and its transmitter up, reads the > panel's EDID over the AUX channel and takes its preferred mode, trains > the link with rate and lane count fallback, programs the video stream > and hands the resulting framebuffer to the video uclass. Failures are > propagated where the reference driver discards them, because DRM can > retry a modeset and a bootloader cannot. > > On removal it hands the link back quiescent: the backlight goes off, the > stream is muted, the panel is put in D3, and the PHY and the panel supply > are turned off. The display domain itself is powered off when the DVO is > removed. > > The driver requests no clock. The transmitter generates its link clock > internally, and CLK_TOP_EDP_SEL, the eDP mux, is the parent of the DVO's > pixel gate, so it is driven through the DVO. > > Signed-off-by: David Lechner <[email protected]> > > diff --git a/drivers/video/mediatek/Kconfig b/drivers/video/mediatek/Kconfig > index 6e9ad26ab54..f26ce979077 100644 > --- a/drivers/video/mediatek/Kconfig > +++ b/drivers/video/mediatek/Kconfig > @@ -57,3 +57,25 @@ config VIDEO_MEDIATEK_HDMI > connected display, selects its preferred mode and drives the > vdosys1 display pipeline (MDP RDMA, padding, merge, ETHDR > mixer, DPI) to scan out the U-Boot framebuffer over HDMI. > + > +config VIDEO_MEDIATEK_EDP
can you sort it? Should go before VIDEO_MEDIATEK_HDMI. Same in the Makefile below > + bool "eDP video path for MediaTek SoCs" > + depends on VIDEO && ARCH_MEDIATEK > + depends on ARM64 && CLK && PHY && POWER_DOMAIN > + select ARM_SMCCC > + select BACKLIGHT > + select DM_REGULATOR > + select I2C_EDID > + select MISC > + select MTK_SMI > + select PHY_MTK_DP > + select SYSCON > + select VIDEO_MEDIATEK_DISP_COMP > + select VIDEO_MEDIATEK_DISP_PIPELINE > + select VIDEO_MEDIATEK_DVO VIDEO_MEDIATEK_DVO already selects VIDEO_MEDIATEK_DISP_COMP and MISC. Do we want to add them here again? > + help > + Enable support for the embedded DisplayPort output found on > + MediaTek SoCs such as the MT8189. The driver drives the vdosys0 > + display pipeline (OVL, RDMA, DVO) and the eDP transmitter, reads > + the EDID of the attached panel over the AUX channel and scans out > + the U-Boot framebuffer to it. > diff --git a/drivers/video/mediatek/Makefile b/drivers/video/mediatek/Makefile > index 3bd69617b74..0f4eb6b5c0f 100644 > --- a/drivers/video/mediatek/Makefile > +++ b/drivers/video/mediatek/Makefile > @@ -28,3 +28,5 @@ obj-$(CONFIG_VIDEO_MEDIATEK_HDMI) += \ > mtk_ethdr.o \ > mtk_hdmi.o \ > mtk_mdp_rdma.o > + > +obj-$(CONFIG_VIDEO_MEDIATEK_EDP) += mtk_edp.o sort -- Julien Stephan <[email protected]>
