Import the power domain definitions for the i.MX7D from the Linux kernel.

Signed-off-by: Nora Schiffer <[email protected]>
---
 drivers/power/domain/Kconfig                  |  6 +-
 drivers/power/domain/imx-gpcv2-power-domain.c | 60 ++++++++++++++++++-
 2 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 2915be0fc76..4c903440c1b 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -34,10 +34,10 @@ config BCM6328_POWER_DOMAIN
          mapped registers.
 
 config IMX_GPCV2_POWER_DOMAIN
-       bool "Enable i.MX8M power domain driver"
-       depends on POWER_DOMAIN && ARCH_IMX8M
+       bool "Enable i.MX7D/i.MX8M power domain driver"
+       depends on POWER_DOMAIN && (ARCH_IMX8M || MX7D)
        help
-         Enable support for manipulating NXP i.MX8M on-SoC power domains.
+         Enable support for manipulating NXP i.MX7D/i.MX8M on-SoC power 
domains.
 
 config IMX8_POWER_DOMAIN
        bool "Enable i.MX8 power domain driver"
diff --git a/drivers/power/domain/imx-gpcv2-power-domain.c 
b/drivers/power/domain/imx-gpcv2-power-domain.c
index d6334d1b8c3..542edb24696 100644
--- a/drivers/power/domain/imx-gpcv2-power-domain.c
+++ b/drivers/power/domain/imx-gpcv2-power-domain.c
@@ -17,6 +17,7 @@
 #include <power/regulator.h>
 #include <wait_bit.h>
 
+#include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
 #include <dt-bindings/power/imx8mp-power.h>
@@ -25,6 +26,12 @@
 #define GPC_PGC_CPU_MAPPING                    0x0ec
 #define IMX8MP_GPC_PGC_CPU_MAPPING             0x1cc
 
+#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN                BIT(6)
+#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN                BIT(5)
+#define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN                BIT(4)
+#define IMX7_PCIE_PHY_A_CORE_DOMAIN            BIT(3)
+#define IMX7_MIPI_PHY_A_CORE_DOMAIN            BIT(2)
+
 #define IMX8M_PCIE2_A53_DOMAIN                 BIT(15)
 #define IMX8M_OTG2_A53_DOMAIN                  BIT(5)
 #define IMX8M_OTG1_A53_DOMAIN                  BIT(4)
@@ -49,6 +56,12 @@
 #define GPC_PU_PGC_SW_PUP_REQ                  0x0f8
 #define GPC_PU_PGC_SW_PDN_REQ                  0x104
 
+#define IMX7_USB_HSIC_PHY_SW_Pxx_REQ           BIT(4)
+#define IMX7_USB_OTG2_PHY_SW_Pxx_REQ           BIT(3)
+#define IMX7_USB_OTG1_PHY_SW_Pxx_REQ           BIT(2)
+#define IMX7_PCIE_PHY_SW_Pxx_REQ               BIT(1)
+#define IMX7_MIPI_PHY_SW_Pxx_REQ               BIT(0)
+
 #define IMX8M_PCIE2_SW_Pxx_REQ                 BIT(13)
 #define IMX8M_OTG2_SW_Pxx_REQ                  BIT(3)
 #define IMX8M_OTG1_SW_Pxx_REQ                  BIT(2)
@@ -90,6 +103,10 @@
  * GPC_PGC memory map are incorrect, below offset
  * values are from design RTL.
  */
+#define IMX7_PGC_MIPI                  16
+#define IMX7_PGC_PCIE                  17
+#define IMX7_PGC_USB_HSIC              20
+
 #define IMX8M_PGC_PCIE1                        17
 #define IMX8M_PGC_OTG1                 18
 #define IMX8M_PGC_OTG2                 19
@@ -150,7 +167,8 @@ struct imx_gpcv2_power_domain_plat {
        int has_pd;
 };
 
-#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MQ)
+#if defined(CONFIG_MX7D) || defined(CONFIG_IMX8MM) || \
+       defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MQ)
 static const struct imx_pgc_regs imx7_pgc_regs = {
        .map = GPC_PGC_CPU_MAPPING,
        .pup = GPC_PU_PGC_SW_PUP_REQ,
@@ -159,6 +177,43 @@ static const struct imx_pgc_regs imx7_pgc_regs = {
 };
 #endif
 
+#ifdef CONFIG_MX7D
+static const struct imx_pgc_domain imx7_pgc_domains[] = {
+       [IMX7_POWER_DOMAIN_MIPI_PHY] = {
+               .bits  = {
+                       .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
+                       .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
+               },
+               .voltage   = 1000000,
+               .pgc       = BIT(IMX7_PGC_MIPI),
+       },
+
+       [IMX7_POWER_DOMAIN_PCIE_PHY] = {
+               .bits  = {
+                       .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
+                       .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
+               },
+               .voltage   = 1000000,
+               .pgc       = BIT(IMX7_PGC_PCIE),
+       },
+
+       [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
+               .bits  = {
+                       .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
+                       .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
+               },
+               .voltage   = 1200000,
+               .pgc       = BIT(IMX7_PGC_USB_HSIC),
+       },
+};
+
+static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
+       .domains = imx7_pgc_domains,
+       .domains_num = ARRAY_SIZE(imx7_pgc_domains),
+       .pgc_regs = &imx7_pgc_regs,
+};
+#endif
+
 #ifdef CONFIG_IMX8MQ
 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
        [IMX8M_POWER_DOMAIN_PCIE1] = {
@@ -580,6 +635,9 @@ static int imx_gpcv2_power_domain_of_to_plat(struct udevice 
*dev)
 }
 
 static const struct udevice_id imx_gpcv2_power_domain_ids[] = {
+#ifdef CONFIG_MX7D
+       { .compatible = "fsl,imx7d-gpc", .data = (long)&imx7_pgc_domain_data },
+#endif
 #ifdef CONFIG_IMX8MQ
        { .compatible = "fsl,imx8mq-gpc", .data = (long)&imx8m_pgc_domain_data 
},
 #endif
-- 
2.55.0

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