Triode wrote:
> I suspect a timing issue too - don't like the look of the udelay in
> here....
>
> >
Code:
--------------------
> >
> ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
> sgtl5000->supplies);
> if (ret)
> goto err_regulator_free;
>
> /* wait for all power rails bring up */
> udelay(10);
>
> /* read chip information */
> reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
> if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
> SGTL5000_PARTID_PART_ID) {
> dev_err(codec->dev,
> "Device with ID register %x is not a sgtl5000\n", reg);
> ret = -ENODEV;
> goto err_regulator_disable;
> }
>
--------------------
> >
Hi Triode or JackOfAll...
The udelay for me is a little like russian roulette...
Would it help to put an insane delay of udelay(1000000) 1 sec here...
It's not the proper way to solve it , but I can test it on both my
boards
and both my sandisk Ultra...
Everyone can wait 1 sec more under boot , and if it solves this issue
, I would be so glad...
Tell me what to do, I can test it if you like...
/Michael
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