Julian, If you are counting samples, you can only do so when both tvalid and tready are simultaneously high at rising clock edge (this will work fine even in the future if you "throttle" the input by controlling tready). Once implemented, this will give you the accurate sample count you're looking for. Rob
On Fri, Apr 23, 2021 at 1:50 PM <[email protected]> wrote: > Jonathon, > > > Only when tvalid is high. The reason why I did not use pload_tready was > because eventually (is not implemented yet) I want to decide when am ready > to receive data. My goal here is to count samples for now, please let me > know your thoughts. > > > Also, I would like to mention that I am using the axis_data_clk and > axis_data_rst. I can see other clock ce_clk which is also specified in the > YAML file as clock domain but I do not see any ce_rst in my block verilog > file, wonder if I am using the right clock for the user logic. > > > Thanks a lot. > > Julian > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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