http://codereview.chromium.org/2878043/diff/1/4 File src/arm/codegen-arm.cc (right):
http://codereview.chromium.org/2878043/diff/1/4#newcode6246 src/arm/codegen-arm.cc:6246: // deferred code. On 2010/07/22 08:11:23, William Hesse wrote:
It looked like some support for register allocation was being added to
ARM. If
there ever are registers that need to be saved and restored when going
to
deferred code, they will be restored when leaving the block, taking
more than
one instruction. Is there a comment or assert that should be added
here, or is
this not a likely possibility.
That is a good question. This follows the pattern of the other inlining. The patching code actually searches for the next branch instruction after the nop (but if there are any we should block the constant pool for more than one instruction I guess). In any case, there are a lot of ASSERTS that will trigger if this goes wrong - we would find code that was not generated for an inline store and the patching code would trigger ASSERTS. I'll commit since this is nothing new and we should look into it. http://codereview.chromium.org/2878043/show -- v8-dev mailing list [email protected] http://groups.google.com/group/v8-dev
