Hi Gilles,

excuse me, but i don't understand why i have to read the register after a write.
In the imx processor manual i didn't find that behaviour.

Where did you find that information ?

Il 04/04/2012 11:45, Gilles Chanteperdrix ha scritto:
On 04/04/2012 11:29 AM, Roberto Bielli wrote:
Hi Gilles,

i have always this big problem but the timer and the avic are programmed
correctly.
There is something else but i don't know what.
In this moment i'm doing another work but soon i want to debug that error.
It is undoubtly a timer ack/program issue. There is no other problem,
the trace is quite clear: the timer is programmed, should tick, but
does not.

I had a look at the imx code again for other reasons, what may be also
missing in __ipipe_mach_acktimer function is a read of the timer status
register. As in:

void __ipipe_mach_acktimer(void)
{
         uint32_t tstat;

         if (timer_is_v2())
                 tstat = __raw_readl(timer_base + V2_TSTAT);
         else
                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);

         gpt_irq_acknowledge();
}

And put that piece of code in mxc_timer_interrupt in the #ifndef
CONFIG_IPIPE section.

You may also want to issue a register read after programming the
compare register. As in:


void __ipipe_mach_set_dec(unsigned long delay)
{
          if (delay>  mxc_min_delay) {
                  unsigned long tcmp;

                  if (!timer_is_v2()) {
                          tcmp = __raw_readl(timer_base + MX1_2_TCN) + delay;
                          __raw_writel(tcmp, timer_base + MX1_2_TCMP);
                          __raw_readl(timer_base + MX1_2_TCN);
                  } else {
                          tcmp = __raw_readl(timer_base + V2_TCN) + delay;
                          __raw_writel(tcmp, timer_base + V2_TCMP);
                          __raw_readl(timer_base + V2_TCN);
                  }
          } else
                  ipipe_trigger_irq(__ipipe_mach_timerint);
}



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Sviluppo Software                                       
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