You could always just try just throwing delays in there just to check it fixes the compile, then at least you know that's the issue. Worrying about making a filter implementation that is both valid and meets timing can then come later.
Good Luck! Jack On Fri, 11 Mar 2016 at 01:52 Nilan Udayanga <g...@zips.uakron.edu> wrote: > Hi Jack, > > Yes, We tried lookahead pipelining as well. Even in that case, it compiled > without the software register. However, when we add the software register, > it failed for timing (similar to the previous design). > > Regards, > Nilan Udayanga. > > On Thu, Mar 10, 2016 at 8:38 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Nilan, >> >> Yeah, I figured that would be a problem... :) >> Does something like this (which i confess I haven't read, but Fig 14 >> looks potentially relevent) help? -- >> http://www.xilinx.com/support/documentation/white_papers/wp330.pdf >> >> Jack >> >> On Fri, 11 Mar 2016 at 01:21 Nilan Udayanga <g...@zips.uakron.edu> wrote: >> >>> Hi Jack, >>> >>> We can not add any more delays to the feedback loop multipliers and >>> adders, since it changes the filter transfer function. However, we can try >>> on distributing corresponding delays over adders and multipliers, without >>> adding separate delays. But, I don't know whether it may change the >>> critical path delay. >>> >>> Regards, >>> Nilan Udayanga. >>> >>> On Thu, Mar 10, 2016 at 8:02 PM, Jack Hickish <jackhick...@gmail.com> >>> wrote: >>> >>>> I think if you can add latency in those multipliers / adders you'll >>>> probably find your problem will go away. It's the blow path that's >>>> breaking, so I don;t think you can get around ijnserting some registers to >>>> split up thje logic stages -- >>>> >>>> >>>> -------------------------------------------------------------------------------- >>>> Slack: -15.890ns (requirement - (data path - clock >>>> path skew + uncertainty)) >>>> Source: >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42/srl_delay.synth_reg_srl_inst/partial_one.last_srl17e/reg_array[27].fde_used.u2 >>>> (FF) >>>> Destination: >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/blk00000006 >>>> (FF) >>>> Requirement: 5.000ns >>>> Data Path Delay: 20.585ns (Levels of Logic = 12)(Component >>>> delays alone exceeds constraint) >>>> Clock Path Skew: -0.245ns (1.869 - 2.114) >>>> Source Clock: adc0_clk rising at 0.000ns >>>> Destination Clock: adc0_clk rising at 5.000ns >>>> Clock Uncertainty: 0.060ns >>>> >>>> Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE >>>> Total System Jitter (TSJ): 0.070ns >>>> Discrete Jitter (DJ): 0.097ns >>>> Phase Error (PE): 0.000ns >>>> >>>> Maximum Data Path at Slow Process Corner: >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42/srl_delay.synth_reg_srl_inst/partial_one.last_srl17e/reg_array[27].fde_used.u2 >>>> to >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/blk00000006 >>>> Location Delay type Delay(ns) Physical Resource >>>> Logical >>>> Resource(s) >>>> ------------------------------------------------- >>>> ------------------- >>>> SLICE_X64Y79.CQ Tcko 0.381 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42_q_net(27) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42/srl_delay.synth_reg_srl_inst/partial_one.last_srl17e/reg_array[27].fde_used.u2 >>>> SLICE_X65Y79.C1 net (fanout=2) 0.584 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42_q_net(27) >>>> SLICE_X65Y79.C Tilo 0.068 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42_q_net(19) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8/std_conversion_generate.convert/Mmux_din[24]_GND_129_o_MUX_41_o11 >>>> SLICE_X62Y79.D6 net (fanout=1) 0.248 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8/std_conversion_generate.convert/Mmux_din[24]_GND_129_o_MUX_41_o1 >>>> SLICE_X62Y79.D Tilo 0.068 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/delay42_q_net(23) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8/std_conversion_generate.convert/Mmux_din[24]_GND_129_o_MUX_41_o13 >>>> SLICE_X61Y81.A6 net (fanout=26) 0.521 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8/std_conversion_generate.convert/din[24]_GND_129_o_MUX_41_o >>>> SLICE_X61Y81.A Tilo 0.068 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8_dout_net_x31(23) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8/std_conversion_generate.convert/Mmux_result221 >>>> DSP48_X3Y30.B7 net (fanout=16) 1.178 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/convert8_dout_net_x31(7) >>>> DSP48_X3Y30.PCOUT8 Tdspdo_B_PCOUT_MULT 3.691 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2/comp0.core_instance0/blk00000001/blk00000005 >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2/comp0.core_instance0/blk00000001/blk00000005 >>>> DSP48_X3Y31.PCIN8 net (fanout=1) 0.002 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2/comp0.core_instance0/blk00000001/sig0000009b >>>> DSP48_X3Y31.P1 Tdspdo_PCIN_P 1.591 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2/comp0.core_instance0/blk00000001/blk00000004 >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2/comp0.core_instance0/blk00000001/blk00000004 >>>> SLICE_X63Y104.C1 net (fanout=1) 2.858 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/mult2_p_net(2) >>>> SLICE_X63Y104.COUT Topcyc 0.338 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm7_4234b2b9fe/delay1_q_net(19) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/blk00000036 >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/blk00000030 >>>> SLICE_X63Y105.CIN net (fanout=1) 0.000 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/sig0000007a >>>> SLICE_X63Y105.COUT Tbyp 0.078 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm6_9c5bc76fb5/block_t_z2_f45dc8cbb6/delay7_q_net(3) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/blk0000002c >>>> SLICE_X63Y106.CIN net (fanout=1) 0.000 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/sig00000076 >>>> SLICE_X63Y106.AMUX Tcina 0.213 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/sig00000072 >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1/comp0.core_instance0/blk00000001/blk00000028 >>>> SLICE_X65Y107.A1 net (fanout=1) 0.593 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub1_s_net(8) >>>> SLICE_X65Y107.COUT Topcya 0.409 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/delay7_q_net(11) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/blk0000003c >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/blk00000028 >>>> SLICE_X65Y108.CIN net (fanout=1) 0.000 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/sig00000072 >>>> SLICE_X65Y108.COUT Tbyp 0.078 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/delay7_q_net(15) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/blk00000024 >>>> SLICE_X65Y109.CIN net (fanout=1) 0.000 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/sig0000006e >>>> SLICE_X65Y109.DMUX Tcind 0.328 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/delay7_q_net(19) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm12_2626363f3e/block_t_z2_f45dc8cbb6/addsub2/comp1.core_instance1/blk00000001/blk00000020 >>>> DSP48_X4Y53.A19 net (fanout=3) 1.904 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/gateway_out2_x2(19) >>>> DSP48_X4Y53.P16 Tdspdo_A_P_MULT 3.826 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/blk00000005 >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/blk00000005 >>>> SLICE_X59Y109.DX net (fanout=1) 1.526 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/sig000000d7 >>>> SLICE_X59Y109.CLK Tdick 0.034 >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1_p_net(0) >>>> >>>> >>>> ears_sbp22_XSG_core_config/ears_sbp22_XSG_core_config/ears_sbp22_x0/ppcm13_dda55e6716/block_z_1_0d8d8d72ce/mult1/comp1.core_instance1/blk00000001/blk00000006 >>>> ------------------------------------------------- >>>> --------------------------- >>>> Total 20.585ns (11.171ns logic, >>>> 9.414ns route) >>>> (54.3% logic, >>>> 45.7% route) >>>> >>>> >>>> On Fri, 11 Mar 2016 at 00:49 Nilan Udayanga <g...@zips.uakron.edu> >>>> wrote: >>>> >>>>> Hi Jack, >>>>> >>>>> Thank you very much for your suggestions. The block t_z2 is a 2nd >>>>> order feedback loop (figure is attached, Even though it shows 3 delays in >>>>> multipliers, it does not have any delays). >>>>> But I don't think this feedback loop may cause that much of delay. >>>>> >>>>> Regards, >>>>> Nilan Udayanga. >>>>> >>>>> On Thu, Mar 10, 2016 at 7:18 PM, Jack Hickish <jackhick...@gmail.com> >>>>> wrote: >>>>> >>>>>> Hi Nilan, >>>>>> >>>>>> It looks like there's a block called (something like) >>>>>> ppcm12/block_t_z2 with a huge logic delay -- from line 135 of the failing >>>>>> twr file -- >>>>>> >>>>>> Data Path Delay: 20.585ns (Levels of Logic = 12)(Component >>>>>> delays alone exceeds constraint) >>>>>> >>>>>> What is this block? It looks like it has some multipliers and adders >>>>>> and stuff... >>>>>> >>>>>> There's also a timing error in the adc yellow block, but my guess is >>>>>> this is just because the place and route tool gave up when it hit >>>>>> impossible constraints elsewhere. >>>>>> >>>>>> Cheers, >>>>>> Jack >>>>>> >>>>>> On Thu, 10 Mar 2016 at 23:49 Nilan Udayanga <g...@zips.uakron.edu> >>>>>> wrote: >>>>>> >>>>>>> Hi all, >>>>>>> >>>>>>> We are having a little weird problem during the compilation of a >>>>>>> roach 2 design with the adc16 block. I have a design for a specific >>>>>>> application. It is well pipelined and we are using ADC interfaces >>>>>>> clocked >>>>>>> at 200 MHz. When I just terminate the output without using any software >>>>>>> registers at the output, there is no timing error (all timing costrains >>>>>>> have been met). And when I compile the design using the software >>>>>>> register >>>>>>> at the output (just a one software register), it has a timing error, and >>>>>>> says the maximum frequency that can be achieved is around 50 MHz. I am >>>>>>> wondering whether it is a problem with the software register or not. >>>>>>> Please >>>>>>> find the following attachments for the .twr and .twx files for each >>>>>>> cases. >>>>>>> >>>>>>> I have tried using snapshots blocks too. Thats giving the same >>>>>>> timing error. >>>>>>> >>>>>>> Your help will be greatly appreciated. >>>>>>> >>>>>>> Regards, >>>>>>> Nilan Udayanga. >>>>>>> >>>>>>> On Wed, Mar 9, 2016 at 4:03 PM, Nilan Udayanga <g...@zips.uakron.edu >>>>>>> > wrote: >>>>>>> >>>>>>>> Hi All, >>>>>>>> >>>>>>>> Thank you very much for all your suggestions. >>>>>>>> >>>>>>>> I have two more questions, >>>>>>>> >>>>>>>> Since, ADCs need to be clocked at 480 MHz for the demux=2 mode, how >>>>>>>> does the FPGA clock at 240 MHz? does it use a clock divider internally? >>>>>>>> >>>>>>>> Is there any maximum operating frequency for the FPGA, when we use >>>>>>>> the adc16 block? >>>>>>>> >>>>>>>> Regards, >>>>>>>> Nilan Udayanga. >>>>>>>> >>>>>>>> On Wed, Mar 9, 2016 at 3:22 PM, Jack Hickish <jackhick...@gmail.com >>>>>>>> > wrote: >>>>>>>> >>>>>>>>> With regards to the demux option, for the system you describe you >>>>>>>>> want -d 2 (I.e. demux by = run the FPGA at half the sample rate, and >>>>>>>>> process two samples in parallel on every FPGA clock cycle). Basically, >>>>>>>>> provided you have the up to date ruby package, all you need to do is >>>>>>>>> run >>>>>>>>> adc16_init.rb with appropriate options, and that will program your >>>>>>>>> roach >>>>>>>>> and set everything up for you. >>>>>>>>> >>>>>>>>> I think the default mode of the adc16 ruby script assumes that, >>>>>>>>> whatever mode you're using the ADC in, the external clock provided is >>>>>>>>> at >>>>>>>>> the sample rate. Though, as Matt added, the ADC supports other >>>>>>>>> dividing >>>>>>>>> options if they're useful to you and you're willing to read the ADC >>>>>>>>> data >>>>>>>>> sheet to work out how to set the divider properties. >>>>>>>>> >>>>>>>>> Cheers >>>>>>>>> Jack >>>>>>>>> >>>>>>>>> >>>>>>>>> On Wed, 9 Mar 2016, 09:49 David MacMahon, < >>>>>>>>> dav...@astro.berkeley.edu> wrote: >>>>>>>>> >>>>>>>>>> Hi Vishwa, >>>>>>>>>> >>>>>>>>>> I am not at my computer right now, so this is from memory, but I >>>>>>>>>> think you want to specify an IP clock rate of 240 MHz and supply a >>>>>>>>>> 480 MHz >>>>>>>>>> clock to the ADC card(s). The IP clock rate is sometimes called the >>>>>>>>>> fabric >>>>>>>>>> clock rate. It is the rate at which the FPGA logic elements (aka >>>>>>>>>> fabric) >>>>>>>>>> operate. The ADC chips need a sample clock that is commensurate with >>>>>>>>>> the >>>>>>>>>> sampling frequency. When you initialize the ADCs using >>>>>>>>>> adc16_init.rb, be >>>>>>>>>> sure to pass the "-d" option. If your version of adc16_init.rb does >>>>>>>>>> not >>>>>>>>>> support the "-d" option, then you will need to update it. >>>>>>>>>> >>>>>>>>>> Hope this helps, >>>>>>>>>> Dave >>>>>>>>>> >>>>>>>>>> On Mar 9, 2016, at 08:33, Vishwa Seneviratne < >>>>>>>>>> mp...@zips.uakron.edu> wrote: >>>>>>>>>> >>>>>>>>>> Hi David/Jack, >>>>>>>>>> >>>>>>>>>> We are working on a beam former and we use the 'ADC16x250-8 coax >>>>>>>>>> rev 2' to sample RF signals using ROACH2-Rev 2. The operating BW is >>>>>>>>>> 240MHz. >>>>>>>>>> Thus, we need to sample the signals at 480 MSamples/s. We have few >>>>>>>>>> queries >>>>>>>>>> regarding the adc16 yellow block and how to setup the input clock. >>>>>>>>>> >>>>>>>>>> 1. Can we compile a design by setting the IP clock rate to 480MHz? >>>>>>>>>> 2. Should we supply a IP clock frequency of 480MHz to the ADC >>>>>>>>>> board to achieve a sampling rate of 480MSamples/s. If not, at what >>>>>>>>>> clock >>>>>>>>>> rate should we supply? And what other parameters needed to setup when >>>>>>>>>> running the bof file. >>>>>>>>>> >>>>>>>>>> Thank you >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Sincerely, >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> *Vishwa Seneviratne* >>>>>>>>>> >>>>>>>>>> *Graduate Student* >>>>>>>>>> >>>>>>>>>> *Dept. of Electrical and Computer Engineering* >>>>>>>>>> *University of Akron* >>>>>>>>>> >>>>>>>>>> On Wed, Feb 3, 2016 at 12:38 PM, David MacMahon < >>>>>>>>>> dav...@astro.berkeley.edu> wrote: >>>>>>>>>> >>>>>>>>>>> Hi, Vishwa, >>>>>>>>>>> >>>>>>>>>>> The software installed by following the ADC16 user guide had not >>>>>>>>>>> been updated with the newer version of the adc16 code that supports >>>>>>>>>>> demux >>>>>>>>>>> mode. I have updated the software that the user guide points to, >>>>>>>>>>> so if you >>>>>>>>>>> reinstall the adc16 gem as per the user guide you should get >>>>>>>>>>> version 0.4.0 >>>>>>>>>>> which supports demux mode. >>>>>>>>>>> >>>>>>>>>>> Thanks for bringing this issue to my attention. >>>>>>>>>>> >>>>>>>>>>> Dave >>>>>>>>>>> >>>>>>>>>>> On Feb 3, 2016, at 7:02 PM, Vishwa Seneviratne < >>>>>>>>>>> mp...@zips.uakron.edu> wrote: >>>>>>>>>>> >>>>>>>>>>> Hi Dave, >>>>>>>>>>> >>>>>>>>>>> Here is the output. >>>>>>>>>>> >>>>>>>>>>> vishwa@server3:~/Desktop/roach/poly$ adc16_init.rb -h >>>>>>>>>>> Usage: adc16_init.rb [OPTIONS] HOSTNAME BOF >>>>>>>>>>> >>>>>>>>>>> Programs HOSTNAME with ADC16-based design BOF and then calibrates >>>>>>>>>>> the serdes receivers. >>>>>>>>>>> >>>>>>>>>>> Options: >>>>>>>>>>> -i, --iters=N Number of snaps per tap [1] >>>>>>>>>>> -r, --reg=R1=V1[,R2=V2...] Register addr=value pairs >>>>>>>>>>> to set >>>>>>>>>>> -v, --[no-]verbose Display more info [false] >>>>>>>>>>> -h, --help Show this message >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> vishwa@server3:~/Desktop/roach/poly$ gem list adc16 >>>>>>>>>>> >>>>>>>>>>> *** LOCAL GEMS *** >>>>>>>>>>> >>>>>>>>>>> adc16 (0.3.6) >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> Sincerely, >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> *Vishwa Seneviratne* >>>>>>>>>>> >>>>>>>>>>> *Graduate Student* >>>>>>>>>>> >>>>>>>>>>> *Dept. of Electrical and Computer Engineering* >>>>>>>>>>> *University of Akron* >>>>>>>>>>> >>>>>>>>>>> On Wed, Feb 3, 2016 at 11:28 AM, David MacMahon < >>>>>>>>>>> dav...@astro.berkeley.edu> wrote: >>>>>>>>>>> >>>>>>>>>>>> What does "adc16_init.rb -h" show? What does "gem list adc16" >>>>>>>>>>>> show? Maybe you need a newer version of the adc16 code. >>>>>>>>>>>> >>>>>>>>>>>> Dave >>>>>>>>>>>> >>>>>>>>>>>> On Feb 3, 2016, at 18:20, Vishwa Seneviratne < >>>>>>>>>>>> mp...@zips.uakron.edu> wrote: >>>>>>>>>>>> >>>>>>>>>>>> Hi Jack, >>>>>>>>>>>> >>>>>>>>>>>> I'm thinking that the ruby script 'adc16_init.rb' does not >>>>>>>>>>>> identify the '--demux' parameter. I used the code at 'git:// >>>>>>>>>>>> github.com/david-macmahon/casper_adc16.git'. What can I do to >>>>>>>>>>>> set the parameter? >>>>>>>>>>>> >>>>>>>>>>>> Thank you >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> Sincerely, >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> *Vishwa Seneviratne* >>>>>>>>>>>> >>>>>>>>>>>> *Graduate Student* >>>>>>>>>>>> >>>>>>>>>>>> *Dept. of Electrical and Computer Engineering* >>>>>>>>>>>> *University of Akron* >>>>>>>>>>>> >>>>>>>>>>>> On Wed, Feb 3, 2016 at 11:02 AM, Vishwa Seneviratne < >>>>>>>>>>>> mp...@zips.uakron.edu> wrote: >>>>>>>>>>>> >>>>>>>>>>>>> Hi Jack, >>>>>>>>>>>>> >>>>>>>>>>>>> I did try all the combinations. The error remains the same. >>>>>>>>>>>>> >>>>>>>>>>>>> $ adc16_init.rb -v --demux=1 192.168.10.5 poly_design.bof >>>>>>>>>>>>> /var/lib/gems/1.9.1/gems/adc16-0.3.6/bin/adc16_init.rb:40:in >>>>>>>>>>>>> `<top (required)>': invalid option: --demux=2 >>>>>>>>>>>>> (OptionParser::InvalidOption) >>>>>>>>>>>>> from /usr/local/bin/adc16_init.rb:19:in `load' >>>>>>>>>>>>> from /usr/local/bin/adc16_init.rb:19:in `<main>' >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> Sincerely, >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> *Vishwa Seneviratne* >>>>>>>>>>>>> >>>>>>>>>>>>> *Graduate Student* >>>>>>>>>>>>> >>>>>>>>>>>>> *Dept. of Electrical and Computer Engineering* >>>>>>>>>>>>> *University of Akron* >>>>>>>>>>>>> >>>>>>>>>>>>> On Wed, Feb 3, 2016 at 2:25 AM, Jack Hickish < >>>>>>>>>>>>> jackhick...@gmail.com> wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>> Hi Vishwa, >>>>>>>>>>>>>> >>>>>>>>>>>>>> Is the syntax definitely -demux=1 andnot either --demux=1 or >>>>>>>>>>>>>> -d 1 ? >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>> Jack >>>>>>>>>>>>>> >>>>>>>>>>>>>> On Wed, 3 Feb 2016, 12:39 a.m. Vishwa Seneviratne < >>>>>>>>>>>>>> mp...@zips.uakron.edu> wrote: >>>>>>>>>>>>>> >>>>>>>>>>>>>>> Hi, >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> I am working on how to work with different operating of >>>>>>>>>>>>>>> the 'ADC16x250-8 coax rev 2' for a very simple design to test >>>>>>>>>>>>>>> how the ADC >>>>>>>>>>>>>>> works. The design is compiled at an IP clock rate setting of >>>>>>>>>>>>>>> 200MHz. My >>>>>>>>>>>>>>> objective is to sample my input signal at higher sampling rate >>>>>>>>>>>>>>> (preferably >>>>>>>>>>>>>>> 400, 800 MHz). >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> According to the user guide '' >>>>>>>>>>>>>>> https://casper.berkeley.edu/wiki/images/4/4c/ADC16_user_guide.txt"; >>>>>>>>>>>>>>> by setting the demux parameter I should be able to switch >>>>>>>>>>>>>>> between different >>>>>>>>>>>>>>> sampling rates. I get the following error. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> $ adc16_init.rb -v -demux=1 192.168.10.5 poly_design.bof >>>>>>>>>>>>>>> /var/lib/gems/1.9.1/gems/adc16-0.3.6/bin/adc16_init.rb:40:in >>>>>>>>>>>>>>> `<top (required)>': invalid option: -demux=2 >>>>>>>>>>>>>>> (OptionParser::InvalidOption) >>>>>>>>>>>>>>> from /usr/local/bin/adc16_init.rb:19:in `load' >>>>>>>>>>>>>>> from /usr/local/bin/adc16_init.rb:19:in `<main>' >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> When I don't pass the 'demux' parameter the ADC board get >>>>>>>>>>>>>>> initialized to 8 analog inputs by default. >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> How do I resolve this issue? or how can I set the ADC's to >>>>>>>>>>>>>>> operate at different sampling rates? >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Thank you in advance >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Sincerely, >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> *Vishwa Seneviratne* >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> *Graduate Student* >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> *Dept. of Electrical and Computer Engineering* >>>>>>>>>>>>>>> *University of Akron* >>>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>> >>>>>>>> >>>>>>> >>>>> >>> >
