Sebastien,
Thank you for the response. I plan to make Migen available for simulation
on EDA Playground (using Icarus Verilog) on Sunday or Monday.
Regarding synthesis,
I won't be able to pre-fill the list of modules using Python since I only
have Javascript available for the front end.
For pre-filling the port list, I don't quite follow your code. (I'm not a
Python expert). Can you give me another example for:
1. Design code (not sure if all these are valid):
class MyModule(Module):
def __init__(self, coef, wsize=16):
self.coef = coef
self.wsize = wsize
self.i = Signal((self.wsize, True))
self.busy = Signal()
self.operands = Sink([("a", 16), ("b", 16)])
self.result = Source([("r", 17)])
# etc.
2. User input:
top_level = MyModule
attributes = 1, 16
3. Generated Verilog conversion script:
from design import *
top = <top_level>(<attributes>)
print(verilog.convert(top, ios={name for name in dir(top) if name[0] != "_"
and
isinstance(getattr(top, name), Signal)}))
The above doesn't work, and I get:
Traceback (most recent call last):
File "design.py", line 16, in <module>
print(verilog.convert(top, ios={name for name in dir(top) if name[0] !=
"_" and isinstance(getattr(top, name), Signal)}))
File "/work/migen/migen/fhdl/verilog.py", line 314, in convert
| ios)
File "/work/migen/migen/fhdl/namer.py", line 203, in build_namespace
pnd = _build_pnd(signals)
File "/work/migen/migen/fhdl/namer.py", line 185, in _build_pnd
groups = _build_signal_groups(signals)
File "/work/migen/migen/fhdl/namer.py", line 172, in _build_signal_groups
cur_signal = cur_signal.related
AttributeError: 'str' object has no attribute 'related'
Thanks,
Victor
On Thu, Nov 28, 2013 at 8:59 AM, Sébastien Bourdeauducq <
sebastien.bourdeaud...@lekernel.net> wrote:
> On 11/27/2013 11:52 PM, Victor Lyuboslavsky wrote:
> > 2. Ask the user to enter the top level Module class and the list of
> > ports. And then I simply run print(verilog.convert(UserModule(),
> > ios{ports})) on the server.
>
> I would be in favor of that. You can pre-fill the list of modules by
> analyzing the source code:
>
> >>> from migen.fhdl.std import *
> >>> from migen.genlib import divider # you can also use importlib (see
> MiSoC make.py for an example)
> >>> {name for name, cl in divider.__dict__.items() if isinstance(cl,
> type) and cl is not Module and issubclass(cl, Module)}
> {'Divider'}
>
> Then after the user has provided any required parameters (you can use
> Python introspection to get the parameter list of the __init__ method),
> you can pre-fill the port list:
>
> >>> top = divider.Divider(5)
> >>> {name for name in dir(top) if name[0] != "_" and
> isinstance(getattr(top, name), Signal)}
> {'divisor_i', 'remainder_o', 'dividend_i', 'start_i', 'quotient_o',
> 'ready_o'}
>
> This code does not cover all cases, but it should be nice for simple
> designs.
>
> Sebastien
>
>
>
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