Hi, On 11/29/2013 10:32 PM, Victor Lyuboslavsky wrote: > That seems to be working. Signals seem to be getting mapped to input > ports. What about output ports -- does the convert method automatically > figure out what is input and output?
Yes, if you assign to IO signals via comb/sync statements or an instance, etc. they will automatically become output ports. > And Sink/Source variables -- are they not synthesizable? They are synthesizable. They are objects that contain other Signals internally; if you want them as port, those internal Signals should be passed into the "ios" parameter of verilog.convert. This is one of the many cases that the simple Signal lister I proposed does not handle. You could make it recognize Record types (of which Source and Sink are derived) to fix this particular problem, or just keep it simple and stupid and let the user deal manually with special cases. It is e.g. possible to have a Python list, set, or dictionary containing port signals. You cannot automatically recognize all possibilities correctly... > What are a couple good example designs that I can try the verilog > conversion on? Look at the divider and cordic: https://github.com/m-labs/migen/blob/master/migen/genlib/divider.py https://github.com/m-labs/migen/blob/master/migen/genlib/cordic.py A more complex design can be the LASMIcon SDRAM bank control FSM: https://github.com/m-labs/misoc/blob/master/misoclib/lasmicon/bankmachine.py Sebastien _______________________________________________ Devel mailing list Devel@lists.milkymist.org https://ssl.serverraum.org/lists/listinfo/devel
