Victor, It looks really great :) Really cool web based tool!
Did you compile iverilog to javascript and run it locally on the user's browser? Or does it run server-side? 2013/11/30 Victor Lyuboslavsky <vic...@victoreda.com> > Migen is now available on EDA Playground for simulations. Example: > http://www.edaplayground.com/s/example/453 > > Please try it out. It works with the waveform viewer. > > It would be good to have a couple more Migen examples, like a memory > example (all the other methodologies have a RAM example). If you'd like to > create a couple good Migen examples on EDA Playground and send me the link, > I can put them on the front page. Also, EDA Playground can complement > existing/future Migen examples/tutorials on the web -- add a [Run It] > button next to the code so that the readers can run/modify the example. > > Sebastien, > Can you add a link to Migen documentation? Something like: EDA Playground > -- run Migen simulations online > > Thanks, > Victor > > P.S. I'll be working on integrating Migen with synthesis flows next. > > > On Fri, Nov 29, 2013 at 3:58 PM, Sebastien Bourdeauducq < > sebastien.bourdeaud...@lekernel.net> wrote: > >> Hi, >> >> On 11/29/2013 10:32 PM, Victor Lyuboslavsky wrote: >> > That seems to be working. Signals seem to be getting mapped to input >> > ports. What about output ports -- does the convert method automatically >> > figure out what is input and output? >> >> Yes, if you assign to IO signals via comb/sync statements or an >> instance, etc. they will automatically become output ports. >> >> > And Sink/Source variables -- are they not synthesizable? >> >> They are synthesizable. They are objects that contain other Signals >> internally; if you want them as port, those internal Signals should be >> passed into the "ios" parameter of verilog.convert. This is one of the >> many cases that the simple Signal lister I proposed does not handle. >> >> You could make it recognize Record types (of which Source and Sink are >> derived) to fix this particular problem, or just keep it simple and >> stupid and let the user deal manually with special cases. It is e.g. >> possible to have a Python list, set, or dictionary containing port >> signals. You cannot automatically recognize all possibilities correctly... >> >> > What are a couple good example designs that I can try the verilog >> > conversion on? >> >> Look at the divider and cordic: >> https://github.com/m-labs/migen/blob/master/migen/genlib/divider.py >> https://github.com/m-labs/migen/blob/master/migen/genlib/cordic.py >> >> A more complex design can be the LASMIcon SDRAM bank control FSM: >> >> https://github.com/m-labs/misoc/blob/master/misoclib/lasmicon/bankmachine.py >> >> Sebastien >> >> >> > > _______________________________________________ > Devel mailing list > Devel@lists.milkymist.org > https://ssl.serverraum.org/lists/listinfo/devel > > -- Yann Sionneau
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