On Mon, Dec 09, 2002 at 09:45:12PM +0000, Keith Whitwell wrote: > Charl P. Botha wrote: > >FWIW, I get those SSE sigfpe's too with my Northwood P4 if I don't set > >MESA_NO_SSE=1. > > There's a fix for this in recent cvs: > > /* Mask out highest bit, which is used by AMD for 3dnow > * Newer Intel have this bit set, but do not support 3dnow > */ > AND_L ( CONST(0X7FFFFFFF), EAX)
I still could reproduce this SIGFPE with yesterday's CVS. I just did a grep though all the .c and .h files in my DRI CVS tree for "Mask out highest bit" but could not find the above. In which file should this be? Thanks, Charl -- charl p. botha http://cpbotha.net/ http://visualisation.tudelft.nl/ ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
