Laurent Gauch wrote: >> Output clock isn't the bottleneck, protocol design is. > yes right, if you get the actual ftdi mpsse and arm debug. But the > Amontec mpsse will comes with new loop function >> I like your initiative to create an open source VHDL design and an >> open host protocol for that VHDL. Where is the source code located? > great if you like.
You didn't answer my question - where have you published your VHDL? >> Unless you're publishing your work under a very open license, >> effectively making your design open hardware, I don't think that you >> will get a lot of help to create the critical part which is actually >> the only thing that would be new compared to several existing (open) >> implementations. > > several existing open implementations with swo ! > so please let me know a full open implementations of jtag swd > supporting swo! I guess you haven't seen the Black Magic Probe. > that was my question !!!!!!!!!!!!! No, your question was if someone would be so kind to provide you with a protocol description for the host communication protocol. //Peter ------------------------------------------------------------------------------ Master HTML5, CSS3, ASP.NET, MVC, AJAX, Knockout.js, Web API and much more. Get web development skills now with LearnDevNow - 350+ hours of step-by-step video tutorials by Microsoft MVPs and experts. SALE $99.99 this month only -- learn more at: http://p.sf.net/sfu/learnmore_122812 _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
