Le 11.01.2013 02:17, Peter Stuge a écrit :
> Laurent Gauch wrote:
>>> Output clock isn't the bottleneck, protocol design is.
>> yes right, if you get the actual ftdi mpsse and arm debug.  But the
>> Amontec mpsse will comes with new loop function
>>> I like your initiative to create an open source VHDL design and an
>>> open host protocol for that VHDL. Where is the source code located?
>> great if you like.
> You didn't answer my question - where have you published your VHDL?
Our new mpsse design is fully compatible with actual mpsse, but we comes 
with new commands which one will be documented on a .pdf. The VHDL core 
will not be open source for now.

>
>>> Unless you're publishing your work under a very open license,
>>> effectively making your design open hardware, I don't think that you
>>> will get a lot of help to create the critical part which is actually
>>> the only thing that would be new compared to several existing (open)
>>> implementations.
>> several existing open implementations with swo !
>> so please let me know a full open implementations of jtag swd
>> supporting swo!
> I guess you haven't seen the Black Magic Probe.

Yes I know. Does it come with SWO ?

and you said "several existing ..." , you only give me one , and this 
one is only for cortex debug, and I do not see any SWO from BMP.


>
>> that was my question !!!!!!!!!!!!!
> No, your question was if someone would be so kind to provide you with
> a protocol description for the host communication protocol.
No. Packet and host communication protocol is not the trouble, as 
explained we have two solutions.
But instead to comment the two solutions you talk me about open source 
issue.
>
> //Peter
>
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