Re: gEDA-user: CERN goes for KiCAD
you all never worried about cern before? why start now? better to just keep focused on your current customers then unknown future additional users. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to find which specific part of a PCB is shorted?
wouldn't it be nice to be able to tell a polygon that it belongs to a net and the have the thermals that disagree highlighted? On Fri, 2011-09-02 at 15:13 +1000, Stephen Ecob wrote: Usually, when I have power and ground shorted, it's because of a via placed some where that was accidentally assigned thermals to the wrong layer. -Ethan +1 Often when this happens I find it easiest to fix in a text editor, it's easier to spot a via connected to too many layers there than in the GUI. Stephen Ecob Silicon On Inspiration Sydney Australia www.sioi.com.au $39 Spartan 6 board with 32MB DDR DRAM ? http://www.sioi.com.au/shop/product_info.php/products_id/47 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem and footprints
I am happy that doc is still useful. Best Wishes to All here at geda, Steve M. On Wed, 2011-08-17 at 08:44 -0500, kqt4a...@comcast.net wrote: On Tue, 16 Aug 2011, Colin D Bennett wrote: On Tue, 16 Aug 2011 15:35:46 -0500 (CDT) kqt4a...@comcast.net wrote: I am sure this has been done to death but I have to ask I am a beginner and the way I am using gschem and pcb is quite awkward I open my schematic in gschem and open pcb Then when I add a component in gschem I switch to pcb to search for a footprint When I find the proper footprint in pcb I switch back to gschem and manually edit the properties to add the footprint name I MUST be doing something wrong You're not doing anything “wrong”. There are many “right” ways of working with gEDA... it allows you the freedom to choose what works best for you. If switching back and forth between pcb and gschem is tedious, then consider the following suggestions as just a few of the possible optimizations you can make to your process. I almost never use pcb's footprint browser. Yes, the default pcb footprint library has a lot of symbols with obtuse names, so it is difficult to find the one you need by name. However, I only use a few of the default footprint library's footprints--for instance: JUMPER4, RESC1608N, CAPC1608N, ... and most of my footprints are custom ones I have created myself. The footprints in my own library have extremely descriptive names and all I need is a file manager window listing the available footprint files and I can pick the correct footprint by name. For instance, here are some footprint file names from my library: ... You should be able to understand the purpose of each footprint by its nae and perhaps a quick Google on the package code or part number. I also occasionally have used footprints from gedasymbols.org. The gedasymbols.org web site has a great interface for searching the footprint library and previewing the footprints. Another thing you can do to save time is to defer footprint attribute assignment until you have the schematic mostly drawn. Then you can do footprint assignment quickly. You can use either gschem or the “gattrib” tool to quickly assign footprints to all symbol instances in a schematic. I highly suggest you become proficient at creating your own footprints since you will often run into new parts without a pcb footprint, and this allows you to keep a consistent footprint style matching your own preference (you might have your own preference about silk screen outline style, etc.). Creating footprints was tedious for me at first, but now after making several dozen, it has become really simple. I just grab a calculator (or the qalculator application), a pencil and paper, and lay out the footprint per the manufacturer's package drawing and recommended land pattern. I usually create the footprint file (*.fp) with a text editor since it's easy to get the exact layout that way, but on occasion I will use pcb to draw the footprints graphically, or make minor edits to hand-made footprint files. Thanks for all the suggestions I tend to think ignoring system libraries is the way for me I am spending too much time searching through thousands of footprints when I only regularly use a few dozen I will create a personal library and copy/create footprints there as needed I have reviewed Footprint creation for the open-source layout program PCB With this in hand I was easily able to modify a footprint for my needs And yes I agree gedasymbols.org is a great place to shop One off topic question When I open a schematic in gschem and it contains an unknown symbol there is a placeholder with an error message But when I import a schematic into pcb it seems to throw away anything that has an unknown footprint Is this just the way pcb works or am I missing something Thanks Richard ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reinventing the wheel
Must it be round? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: translation standards (was: fritzing )
I believe the electronics industry has already centered on the PADs ASCII file format which has the netlist, components, foor print's, layers, lines, vias etc. I have bumped into pcb and assembly shop requests for this a few times where they use the information for programming their pick and place equipment as well as their flying probe testers. Plus if you wan't to translate projects back and forth between commercial cad programs this seems to be the most commonly supported format. Steve Meier On Wed, 2009-05-13 at 16:01 -0500, John Griessen wrote: al davis wrote: My proposal does consider placement, which should be enough. It is essentially a netlist format. That's the idea. How about having a netlist format that holds footprint center, plus pad/pin centers that are defined as center of main part of a pad and center of hole circles, and also pad numbers? That would make a netlist skeleton version of a footprint. I think Brendan of the fritzing project wants the descriptive artwork lines too, though. Those could be defined by a generic standard as vector line segments relative to a center zero easily enough. For centroid based drawings like pcb and RS274-X use, a line width number would be part of it too. But then when you get to square pads that are based on a zero length line segment what do you do? Most 3D models used now are edge and surface based, or if 2D like postscript, edge and outline based. Square pads suggest using outline based graphics and round suggests centroid based, so a standard would need both. Defining outline based graphics in output to the standard format would mean any other importing to centroid based would need to convert, and them you get into questions of can you do it losslessly? John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC UI mockup
Good: I like the arrows showing the problem. Wrong location: The reason (i.e. Annular rings that are too small may erode during etching) belongs in the area that you establish the design rule check guidelines. Steve Meier On Sun, 2009-03-29 at 16:21 +0100, Peter Clifton wrote: Hi guys, This time the screen-shot eye-candy is purely made in GIMP, sorry.. but please take a look at it and see if it looks useful... http://www2.eng.cam.ac.uk/~pcjc2/geda/drc_mockup.png It is based on a mixture of UI from the Banshee music player, some of my own ideas for presentation, and the DRC report Ben got from Sierra (including some stolen text which we can't reuse verbatim!) There isn't a great deal of info on the violation shown, hopefully zooming to it obviates the need to take up screen-space with coordinate readouts. (I'd imagine a tooltip, or Details pane might make a nice addition if this was required). Perhaps we could complement this expanded list with an alternative compact view, where the preview image shrinks to a smaller size (or uses a generic icon for the given rule), and we drop the detailed explanation text from each line. Any per-rule processing could be done in a few ways: * Popup click context menu * Add checkbox against each rule, then put action buttons at the bottom - Select all - Deselect all - Ignore selected violations - Highlight selected violations (on layout) - Auto-fix (right along there with Auto-design my circuit ;)) If there was too much information per violation, we could adopt a more eog image viewer approach to properties (similar to our current implementation). Make a dialog with all the information, fix suggestions, actions for a single violation, then put Previous and Next buttons at the bottom. NB: Unfortunately, I don't have a lot of time to develop these ideas in terms of code at the moment, so don't expect to see this on my branch any time soon! Best regards, ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Bad news about gEDA's participation in GSoC 2009
Notice that BRL CAD did make the cut. Why solid modeling but not EDA? On Thu, 2009-03-19 at 11:41 -0500, John Griessen wrote: Stuart Brorson wrote: Hello -- I am unhappy to announce that the gEDA Project's application to the Google Summer of Code was turned down this year. This year, Google says that they are accepting fewer mentoring orgs so that they may concentrate on inceasing the number of students staffing those projects which they accept. Hmmm the top of the new list, the ones new to GSOC, include many web, media, communication developments -- kinda like Google... I guess Google feels less techie electronics is OK in a recession... and probably for any time they care about, being a software oriented company using only very generic hardware, or large well financed arrays of any hardware that is custom for their apps. but they miss that gEDA tools have a creativity amplifying effect on into the next boom indefinitely. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB thermal width
One issue we ran into was that certain plastic connector with pogo pins had such a low melting temperature that heat applied for more then a couple of seconds caused the plastic to melt enough to suck the pogo pin down so that it no longer protruded above the plastic. The amount of time that heat has to be applied to a pin is dependent on the size of the effective heat sink. Seems to me that a single formula for calculating thermals is to restrictive. Steve Meier On Mon, 2009-03-16 at 07:58 -0400, Ethan Swint wrote: IIRC, it has to do with both the annulus width as well as the clearance width. -Ethan Duncan Drennan wrote: In the PCB manual it says, Thermal [Scale] Scale Relative size of thermal fingers. A value of 1.0 makes the finger width twice the annulus width (copper diameter minus drill diameter). The normal value is 0.5. So theoretically making the annulus larger (with s) should make the thermal spoke width larger, but when you do this the thermal width stays constant. Has this definition changed? How is the thermal width currently calculated? Thanks, Duncan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trace impedance calculations in PCB
Take a look at: http://sourceforge.net/project/screenshots.php?group_id=201957 I think it would be cool to be able to select a couple of traces from pcb and insert their info into an application like the above. perhaps have some code that would follow the traces and every time one of the traces, changed direction or width or layer, re-run the calculation and then build a model of a TDR. On Thu, 2009-02-12 at 10:51 -0600, John Griessen wrote: Jeffrey Gregory wrote: Are there any plans to add trace impedance calculations to PCB? Not concrete ones yet that I've heard. If not, is there an argument against it or just that no one has time Time, the avenger. What alternatives do people use? Some pcb action commands can get you a per trace extraction to calculate simple area from, then apply heuristic mapping to lumped param model of the line(s) in other tools. There's pondering of not-existing-yet speedup tools like gsch2cap, pcb2cap that will extract from schematic to gnucap, pcb layout to gnucap based on selection and choice of capacitance model to use. No one's thinking of extracting shapes of trace loops and modeling mutual inductance, if that's what you mean... John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
This is a chicken and egg problem. With revenue in the billions the major eda tool companies have far more resources to keep developing capabilities. On Fri, 2009-01-30 at 10:23 -0700, John Doty wrote: On Jan 29, 2009, at 11:40 PM, Steve Meier wrote: Let us be clear on this concept. The EDA market place is in the 4 to 5 billion dollar range per year. http://www.eetimes.com/news/design/business/showArticle.jhtml? articleID=175701340 You can do all the gorilla marketing that you want to end users who are tied to the dominant tool sets, but it won't do you any good. When Jobs and Wozniak were tinkering in that garage, the dominant computer hardware was System/370. They were wise not to try to compete with that. jobs and woz used a disruptive technology (the integrated circuit) to compete with the bigger hardware. If you want to get these users to move to another tool set there has to be a migration path and an interoperability path. gEDA's interoperability at the netlist level is better than any other thing I've seen. Nobody has solved graphical interoperability here, and gEDA won't either. geda and pcb lag far behind in interoperability with other layout programs and with vendor support for capabilities such as programming their flying probe testers. The issue isn't, is geda or kicad technologically competitive tools, the issue is can users move designs back and forth from the established eda tools and the free tools? If you answer yes then you reduce the risk of the users if you answer no then the safe action of the users is to stick with the tools that they know. I think it's silly to think gEDA can go after the users who are locked in to the big tools. gEDA's natural users are those who are locked out by the high prices. Students, startups, part timers, ... If we give people a tool that gives them the leverage to do big jobs with small resources, the ones with small resources will adopt it, they'll thrive, and gEDA will ride to success on their coattails. sure for isolated developers but it is far harder to work with larger organizations that want your files in the dominant eda file formats. Would open office be as big a player if it couldn't handle doc and xls files? John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
When Jobs and Wozniak were tinkering in that garage, the dominant computer hardware was System/370. They were wise not to try to compete with that. jobs and woz used a disruptive technology (the integrated circuit) to compete with the bigger hardware. And FOSS is disruptive technology, for sure. FOSS is a disruptive technology when you have a large number of developers, Each working part time or being payed from their job. This isn't the case with geda. geda and pcb lag far behind in interoperability with other layout programs and with vendor support for capabilities such as programming their flying probe testers. I've never used pcb, so I can't comment. But gEDA is a great front end to every layout flow I've encountered. I agree the geda works as a front end tool. But you can't take a geda schematic and send it to an orcad user and do them any good. Nor can you take an orcad file and use it. This is a very tall wall which stops people from being able to work together. Would open office be as big a player if it couldn't handle doc and xls files? Different game. The big tools can't even interoperate with each other: ever try to exchange a design with EDIF (shudder)? A different game? I think not. See the tall wall discussion above. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
John, Mentor Graphics provides schematic and board level translators www.mentor.com/products/pcb/pads/translators Altrium does as well and did about 55 million in sales last year. https://wiki.altium.com/display/ADOH/Moving+to+Altium+Designer+From +OrCAD Steve Meier On Fri, 2009-01-30 at 13:53 -0700, John Doty wrote: On Jan 30, 2009, at 12:23 PM, Steve Meier wrote: When Jobs and Wozniak were tinkering in that garage, the dominant computer hardware was System/370. They were wise not to try to compete with that. jobs and woz used a disruptive technology (the integrated circuit) to compete with the bigger hardware. And FOSS is disruptive technology, for sure. FOSS is a disruptive technology when you have a large number of developers, Each working part time or being payed from their job. This isn't the case with geda. Well, I don't know. gEDA is certainly empowering me in a pretty radical way. But of course, you always have to use the strength of the tool, not fight against it. geda and pcb lag far behind in interoperability with other layout programs and with vendor support for capabilities such as programming their flying probe testers. I've never used pcb, so I can't comment. But gEDA is a great front end to every layout flow I've encountered. I agree the geda works as a front end tool. Better than anything else around, I think. That's a major strength we should build upon. But you can't take a geda schematic and send it to an orcad user and do them any good. Never could take a Viewlogic schematic and send it to an Orcad user either. So there's nothing new here. Nor can you take an orcad file and use it. This is a very tall wall which stops people from being able to work together. Even the major commercial tools can't break down each other's walls. Would open office be as big a player if it couldn't handle doc and xls files? Different game. The big tools can't even interoperate with each other: ever try to exchange a design with EDIF (shudder)? A different game? I think not. See the tall wall discussion above. Would you think it important to get TeX to read Word files? Versatile, effective toolkit versus bloated, inefficient tool. I hope gEDA stays versatile and effective. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
What I have been talking about is interoperability. How users can share projects even though they use different tools. GEDAs lack of exporting and importing limits the projects that a consultant can use it for. PCB's lack of exporting the pads ASCII makes it more difficult for assembly shops to programmer their flying probe tester. (translating PCB to and from pads ascii is one of my side pprojects) Steve Meier On Fri, 2009-01-30 at 16:55 -0700, John Doty wrote: These are importers, but you were talking about exporters before. But yes, there's more support for interoperabilty than I knew about. On Jan 30, 2009, at 2:28 PM, Steve Meier wrote: Mentor Graphics provides schematic and board level translators www.mentor.com/products/pcb/pads/translators Altrium does as well and did about 55 million in sales last year. Hmm, if they have a price on their site at all it's buried, suggesting big $$. If they're comparable to their competitors, $55 million is only a couple of thousand seats. gEDA may actually have more users than they do, as widely distributed as it is. So what are we worried about here, exactly? https://wiki.altium.com/display/ADOH/Moving+to+Altium+Designer+From +OrCAD This thread and others make me worry that we don't appreciate what we have in gEDA. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
Specifically, exporting netlists to just about any other tool is a radical strength. That's a *specific* problem, of narrow interest Where as I WAS! (and will no longer) talking about the general issues of having to share work with others like open office can with MS office. Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
John, If there exist two tools each that can import from the other then they can communicate. If person A can only speak German but can understand French and Germen. And person B can only speak French but can understand French and German then they can talk just fine. On Fri, 2009-01-30 at 18:32 -0700, John Doty wrote: On Jan 30, 2009, at 6:16 PM, Steve Meier wrote: Specifically, exporting netlists to just about any other tool is a radical strength. That's a *specific* problem, of narrow interest Where as I WAS! (and will no longer) talking about the general issues of having to share work with others like open office can with MS office. But *nobody* can do that in the EDA world. The commercial tools you mentioned can only import, not export. And (as an open office user) I would not want open office to be a model for gEDA: it copies all of the bloat, inflexibility, and bizarre, unpredictable behavior of the MS software it replaces. Its *only* advantage is that it's free. But gEDA is a superior toolkit. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Guerilla marketing...
GEDA is a Shark in a very small pond. On Fri, 2009-01-30 at 18:32 -0700, John Doty wrote: On Jan 30, 2009, at 6:16 PM, Steve Meier wrote: Specifically, exporting netlists to just about any other tool is a radical strength. That's a *specific* problem, of narrow interest Where as I WAS! (and will no longer) talking about the general issues of having to share work with others like open office can with MS office. But *nobody* can do that in the EDA world. The commercial tools you mentioned can only import, not export. And (as an open office user) I would not want open office to be a model for gEDA: it copies all of the bloat, inflexibility, and bizarre, unpredictable behavior of the MS software it replaces. Its *only* advantage is that it's free. But gEDA is a superior toolkit. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GTK RANT
Yes they are two keys but they are struck simultaneously. If you use two fingers simultaneously to close two holes on a flute is that one note? If use two fingers to alternate between two holes you get two notes. This is all about efficiency. I can hit control C and control v with one hand in one motion. To hit shift h and then d to descend a hierarchical structure takes two key strikes. Steve Meier On Tue, 2009-01-27 at 19:06 +, Peter Clifton wrote: On Tue, 2009-01-27 at 18:55 +, r wrote: *Personally*, I'm not a big fan of two-key shortcuts. They tend to slow down navigation and editing quite a bit. OTOH, I don't care much about less frequent actions - I wouldn't even mind if these were only accessible from the menu. Ctrl + C / Ctrl + V are two key actions surely? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Keyboard shorcuts [WAS: Re: GTK RANT]
No Peter NO DJ might just design a keyboard with keys as small as 1005s just to see who could use it. Steve M. On Wed, 2009-01-28 at 00:08 +, Peter Clifton wrote: On Tue, 2009-01-27 at 18:40 -0500, Dan McMahill wrote: Peter Clifton wrote: The 10 most common actions/operations were accessed by single L-key keypresses. You could zoom in/out, pan, etc all just with the mouse without moving the pointer away from your active layout area. Not beginner friendly but you could cruise in that tool! You rarely needed to move your left hand away from that one spot on the keyboard and your right hand stayed on the mouse and there wasn't much superfluous mouse motion. Right, next hardware project for DJ then... design a build-it-yourself kit to build USB HCI HID device with a row of buttons for driving PCB ;) Kindof like this one for driving Windows: http://www.mustap.com/funzone_post_76_best-microsoft-keyboard ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Keyboard shorcuts [WAS: Re: GTK RANT]
can a 101 key keyboard fit on the paper strip of a paper match? On Tue, 2009-01-27 at 18:25 -0800, Steve Meier wrote: No Peter NO DJ might just design a keyboard with keys as small as 1005s just to see who could use it. Steve M. On Wed, 2009-01-28 at 00:08 +, Peter Clifton wrote: On Tue, 2009-01-27 at 18:40 -0500, Dan McMahill wrote: Peter Clifton wrote: The 10 most common actions/operations were accessed by single L-key keypresses. You could zoom in/out, pan, etc all just with the mouse without moving the pointer away from your active layout area. Not beginner friendly but you could cruise in that tool! You rarely needed to move your left hand away from that one spot on the keyboard and your right hand stayed on the mouse and there wasn't much superfluous mouse motion. Right, next hardware project for DJ then... design a build-it-yourself kit to build USB HCI HID device with a row of buttons for driving PCB ;) Kindof like this one for driving Windows: http://www.mustap.com/funzone_post_76_best-microsoft-keyboard ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: german article in the linux magazin online now
I have a couple of farthings to toss out. The big fish in the eda pond isn't Eagle and it certainly isn't KiCAD. It is ORCAD and Mentor Graphics. GEDA developers should be aware that there are other fish out there but they/we should focus on our strengths. Yes geda is flexible and with each iteration more so. This is a strength that allows power users to warp the gui and the internal geda interoperability. As Peter said you don't like the key bindings then change them. As DJ et al have allowed if you don't like the pcb gui then write another hid. But a documented best/uniform interface practice manual might be worth while as long as flexibility isn't lost. Back to that big fish... I can think of three key ways to hook its users they are interoperability, interoperability and interoperability. To get a real toe hold, become the go to free (beer and speech) tool for converting from Orcad to KiCAD or Eagle. Then everybody in the free software world will have to install geda. Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OT] gEDA Linkedn group
I think geda groups should be where geda users are. Linked in has the advantage of being able to see which companies geda users work for and who they work with. This might be the start of a way to market geda into larger stronger engineering organizations. From my perspective. Sourceforge is about the code, features, bugs and documentation. Facebook and linkedin are about the people. Steve Meier On Sat, 2009-01-24 at 19:37 +, Peter Clifton wrote: On Sat, 2009-01-24 at 18:51 +0100, Giuseppe Dia wrote: Hi there, thanks for your prompt answer. Didn't want to stir a debate on the FAQ execerpt... I think Steve is right, so in the meanwhile I removed the said statement, for a more general one, without quoting or linking to the gEDA website, until a word of the project leader. If Ales and the other feel it's right to continue using it, we may choose together the best description for the group, and choose to modulate the description to give a link strength to gEDA as strong as we want (even none, if you wish, of course). This should by no means become a way of creating tension: to me is just another way to possibly create useful comunication and some visibility for gEDA, and another way to reach EDA professionals who aren't reading this list but may catch some interesting chat there and get involved. Bye, This group is only useful if anyone is using it. Currently gEDA's presence is spread between seul.org, sourceforge.net, launchpad.net, now linkedn.. Do we need a facebook group? I'm actually concerned that if we have so many presences, we end up diluting the brand, and if these aren't actively looked after / maintained, it ends up looking like the project is less active than it really is. In short.. if you create these groups, please be sure to keep them maintained, and ensure they aren't somewhere which people try to get in touch, but get neglected / ignored. Letting us know you created the group is good. Asking before hand would have been better. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OT] gEDA Linkedn group
On Sat, 2009-01-24 at 19:37 +, Peter Clifton wrote: Letting us know you created the group is good. Asking before hand would have been better. Should a group of Chelsea fans have to ask the football club for permission before starting a fan club? In my book no. They just shouldn't call themselves the official whatever fan club or use the copyrighted work of others without their permission. Can you imagine if every linux user group had have Linus's blessing? Poor Linus would be over whelmed. Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OT] gEDA Linkedn group
so what is off topic? 1) a linkedin group associated with the geda project? or 2) what the mission statement of the geda group is? or both? In my opinion this hasn't moved so far astray that it isn't associated with the use and users of geda. For example if social organizations being constructed around the users of geda is off topic then shouldn't free dog meeting announcements also be off topic? My suggestion would be for a group that wishes to organize around a project would be to ask that project leader if they can just use the description from off of the web site. Funny enough just this afternoon, I was contemplating this same issue (starting a linkedin group) for a mountaineering club I have long been a member of. Steve Meier On Fri, 2009-01-23 at 21:51 -0500, Ales Hvezda wrote: [snip] OK, but you can see where this idea creeps in: people wanting to work on, contribute to, and use Free (as in freedom) hardware designs do not want to depend on proprietary software to do it. Exactly, which is the primary reason why I started the gEDA project. Maybe Giuseppe should weaken that statement a little, but it makes sense to keep some kind of reference in there. Maybe: The statement actually comes for the gEDA website and the wording was choosen quite explicitly: The gEDA project was started because of the lack of free EDA tools for POSIX systems with the primary purpose of advancing the state of free hardware or open source hardware. ... The key words are: The gEDA project was started because ... Also, this license page has been debated and refined in the past: http://geda.seul.org/license.html and if you want to argue against it, then by all means, but please do it offlist. Thanks, -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [OT] gEDA Linkedn group
;) I did and responded before you did. Steve M. On Fri, 2009-01-23 at 22:39 -0500, Ales Hvezda wrote: [snip] so what is off topic? Very little it seems. If you read my e-mail again, I didn't say anything was off topic. I just don't want to see another debate on the license, since it is all in the archives. And if you want to lobby for a change, please do it off list. -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Fritzing was: Re: geda-user Digest, Vol 32, Issue 92
This reminds me of two facts of saturation magnetic recording on rotating (disc) media. You can only have an even number of transitions around a track. Also, as much as test engineers would like to both surfaces have to be spun at the same rpm. On Thu, 2009-01-22 at 13:02 -0500, DJ Delorie wrote: *chuckle* Right now, PCB doesn't quite support single sided boards. (Stuart waits for others to explain how he is wrong again) Since you insist... There's no such thing as a one-sided board. Boards always have at least two sides, unless you've invented a mobius pcb. Therefore, pcb supports two-sided boards with copper only on one side, which is what people actually make. :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC 6/6] Generation of log files
I was thinking that the question was should the log file be deleted at the completion of the program execution. If a new user is required to go back and re run the code but change a setting you might be forever telling new users to do so. By having a no error delete of the log file a good run would clean up for a previous bad run. Steve Meier On Sat, 2009-01-17 at 07:37 +, Peter TB Brett wrote: On Saturday 17 January 2009 02:43:44 Steve Meier wrote: hmmm, isn't problem info being logged. I would agree if during the current run the logfile only included warnings. 99+% of the time, the log doesn't contain anything other than a copywrite/no-warranty notice and a list of files loaded. how about if at the end of execution that if there was a problem of some class detected that the user be asked if the log file should be retained? How about if something goes wrong, the user could re-run with logging enabled? I guess another alternative is that we could make the default logging destination: $HOME/.gEDA/logs/ And just have a single gschem.log, gnetlist.log, etc. Peter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC 6/6] Generation of log files
Amen On Sat, 2009-01-17 at 10:56 -0500, Ales Hvezda wrote: Currently, running any gEDA suite program leaves behind a log file in the current working directory. I would like to change the default to not generating log files, so that I (and other users who use the default configuration) don't end up with gschem.log and gnetlist.log files scattered over their entire filesystem. Any objections? No objections, but the first user who posts a mysterious error report with no information (where the clarifying info would be in the disabled log file), you get the honor of playing 20 questions and telling them how to enable the log file and dealing with all the whining which will result. -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC 6/6] Generation of log files
hmmm, isn't problem info being logged. I would agree if during the current run the logfile only included warnings. how about if at the end of execution that if there was a problem of some class detected that the user be asked if the log file should be retained? On Fri, 2009-01-16 at 18:32 -0500, Dave McGuire wrote: On Fri, January 16, 2009 5:45 pm, Peter TB Brett wrote: Currently, running any gEDA suite program leaves behind a log file in the current working directory. I would like to change the default to not generating log files, so that I (and other users who use the default configuration) don't end up with gschem.log and gnetlist.log files scattered over their entire filesystem. Any objections? Absolutely, positively NO objection here. :) -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC 6/6] Generation of log files
To me the idea of a app.log associated with a project is that if some step in the project goes GAK I would like to know why. For example I modified an altera project and built it and in doing so generated a fubar.ptf file which I then put onto a memory stick and moved fubar.ptf from a windo$e machine to a linux machine :) and then my friend tried to rebuild the embedded linux kernel that matches the board and the linux build went GAK. An engineer asked me why I had built a corrupted fubar.ptf? Well seems that fubar.ptf was fine except that in moving it from the windo$e box to the linux box :) the owner of fubar.ptf became root and no one else had read or write or execute permission and the build of the embedded linux kernel said hey I need that file and I am not allowed to read it so I am going GAK. Would have saved me 30 seconds if a log file had said file access problem and might have saved me the aforementioned accusation of generating corrupted files if my compatriots had had and had known how to read project build log files. A modern fable by Steve Meier On Fri, 2009-01-16 at 19:53 -0700, John Doty wrote: On Jan 16, 2009, at 7:43 PM, Steve Meier wrote: hmmm, isn't problem info being logged. I would agree if during the current run the logfile only included warnings. how about if at the end of execution that if there was a problem of some class detected that the user be asked if the log file should be retained? In UNIXy systems, there's syslog() for this. On systems where there is no such facility, the users probably won't be bothered if gEDA doesn't log stuff. Grist for configure... On Fri, 2009-01-16 at 18:32 -0500, Dave McGuire wrote: On Fri, January 16, 2009 5:45 pm, Peter TB Brett wrote: Currently, running any gEDA suite program leaves behind a log file in the current working directory. I would like to change the default to not generating log files, so that I (and other users who use the default configuration) don't end up with gschem.log and gnetlist.log files scattered over their entire filesystem. Any objections? Absolutely, positively NO objection here. :) -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: [RFC 5/6] Use of X server clipboard
John, For a simulator, wouldn't you want to select a section of a schematic and say simulate this? I think, thinking about scenarios leads to requirements. So to say be able to select an area of a schematic and then transmute that schematic section into the needs of the next application. If the next application doesn't support the paste then of course I would like that LOGGED. Steve Meier On Fri, 2009-01-16 at 21:25 -0700, John Doty wrote: On Jan 16, 2009, at 8:48 PM, DJ Delorie wrote: A program should do one thing well. Capturing circuit information (regardless of what that is) and providing that to a layout system (regardless of what *that* is) is that one thing here. As stated by you, that's two things. Sigh. I'll try to word it as one thing. Be a design capture front-end for layout systems. Please don't get all anal-retentive on me. That's still not one thing, or will pcb support ASIC layouts in the future? Furthermore, we want gschem to be a front-end for simulation systems. And what is the IEC60417 symbol library for? gschem does one thing well but that one thing goes far beyond what pcb or any other program can serve as back end for. That's how well factored, flexible software works. Yes, let's not set our scope too narrow. Specializing on the gEDA- pcb flow is exactly the sort of narrow scope I wish to avoid. That's not what I meant, and you know it. I get enough of that crap at work, I don't need it here too. But I don't know that. I fear gEDA is evolving toward specific scenarios that don't reflect the needs of my projects. And despite the best intentions of the developers, being scenario-driven will inevitably reduce gEDA's flexibility. That's what happens as software evolves, but it happens faster if nobody digs in their heels a bit. gschem should specialize at being a way to get circuit designs from the user's brain to a layout system. Too far. gschem should capture topology. That's what a schematic represents. Layout is a separate problem. Geometry and topology are distinct mathematical concepts for good reason. I don't care which layout system it is, but once the user has chosen one, gschem should integrate with it fairly well. If the user copies from gschem and pastes in pcb, it should do the right thing for feeding information into pcb. I don't care if it's the gschem executable, some scheme script, a callout to gnetlist, or email to your mother's neighbors that makes it happen. I just want it to happen, and I want it to appear seemless and obvious to the user. Please don't minimize the subtlety and complexity here. This is not trivial, and is certain to have adverse consequences for flexibility that we cannot anticipate. But most combinations of a well-factored set of tools will work. If gschem has to use a bunch of specialized do only one thing well helpers, so be it. I just don't think it's right to expect all the users to know how to run each program separately. gschem should have enough hooks in it to allow any layout system to (somewhat) seamlessly integrate with it, through whatever helpers and middleware are needed. Users shouldn't have to exit gschem, run gattrib, exit that, run gsch2pcb, run pcb, exit that, run make, run gschem again, ad infinitum. They *can* but they shouldn't *have to*. Exit? Not necessary. Just a window per GUI and a window for make. but gEDA-Osmond is working so well for my MIT projects that it makes me wonder. So use Osmond, I don't care. You should be able to copy/paste from gschem to Osmond too, and have the right footprint show up there. Or did you want a separate gschem_to_osmond_gui_cut_paste program to do that for you? No, I want to keep separate things separated. Edit schematic in gschem, fs, make, layout in Osmond (or mail design files to the Osmond expert). I don't expect radical cut and paste to work. Mathematica (one of my favorite tools) tries that, and often fails, although Wolfram has vastly more resources than we do. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Do either of you think that one size shoe should fit all peoples feet? The market place of jobs will have opportunities for specialists and for generalists and for ranges in between. The generalist will be at a disadvantage when faced with a task that pushes state of the art for a specific field. The specialist tends to be pressed when outside their area. How does this relate to geda? Feed back from specialists isn't bad but they need to understand that their suggestions will be treated as suggestions not as mandates. The coders will work on what interests them, or what they get payed to work on, or maybe if they get some thrill from being the one to provide some feature (or in DJ's case I think he just can't help but be creative). Steve M. On Thu, 2009-01-15 at 09:43 -0700, John Doty wrote: On Jan 15, 2009, at 9:21 AM, Joerg wrote: Thing is, my jobs aren't simple. They are simpler than you think. A team of specialists can take weeks to do a 20 minute job. I cannot possibly build a whole ultrasound machine or a complete aircraft all by myself. No, but remember that every big job is composed of a large number of small jobs. Many of these small jobs cross specialization boundaries. If you turn the small jobs into big jobs because *you* won't cross such boundaries, the difficulty of the whole job blows up to enormous proportions. The HETE-2 burst alert communication network cost 1/100 what NASA's cost experts said it should. None of its designers was a communication specialist. Go figure... John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
John, That was eloquently said. I would suggest that geda/gaf users at a minimum should attempt to understand the scripting language scheme and its interface to gaf. Steve Meier On Wed, 2009-01-14 at 20:30 -0700, John Doty wrote: On Jan 14, 2009, at 6:43 PM, Joerg wrote: But I can only say it from the position of a user, not as a programmer because that's the domain of the experts here. Back in 1969, I was taught that the purpose of Fortran was to erase this distinction, putting the power of the computer into the hands of the those who really understand the problems to be solved. I remain of the opinion that this is a destructive distinction to make. This tradition is alive and well in programming languages like Perl and Python (and Fortran is still used by many scientists). gEDA is part of this tradition. If, instead, you see yourself as the sort of user who is merely a consumer of programming, I think gEDA will never satisfy you. I also believe that the future of mixed- signal engineering will belong to those who can combine skills in applied physics with programming, as software moves into areas traditionally handled by circuits, and the complexity of designs exceeds the capacity of humans to handle without computer assistance. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
Well ~25 years ago, you didn't need no stinkin layout program you just wire wrapped from the net list which was hand generated. I still have holes in my fingers from those bloody pins. On Tue, 2009-01-13 at 16:00 -0500, DJ Delorie wrote: Sure, but I don't think that's what gEDA was meant to do. But geda *was* meant to be able to hook in other sources of data. Ok, if gEDA is geared towards ASIC/FPGA that's different. It's not - *his* work is geared towards it, and he had a way to make geda work smoothly with his data needs. Each geda user is going to have a preferred way of doing things, and geda needs to be amenable to all of those. *Some* will be defaults, but others may need some custom geda setups to flow smoothly. Wow. With CAD? My first CAD exposure was Racal-Redac on a VAX but being Oh crap, now we're reminiscing. 20 years ago I started with Data General's internal CAD system on D470C terminals. A few years later we switched to Cadstar, and a long hiatus later, I'm using gEDA. young I could only get after-midnight time slots so I resorted to vellum and ink pens. mmm... pens, stickers, and FeCl from Radio Shack. That was about 30 years ago for me. I still have some of the stickers, too. Again, I don't want it to cater to me. I might never use gschem, just wanted to give feedback. What about PCB, though? That runs on Linux/Mac/Windows too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power (and other non-graphical) pins
I don't see why the slotdef attribute can't have a grammar such as slotdef=2:1~v,2~v,13~v,7~h,14~h which says show pins 1, 2 and 3 but hide the fourth and fifth pin following pins. I don't see how this type of change would reduce flexibility. Ales, Where on http://geda.seul.org/wiki/geda:faq is the word goal even used? The word is approach is only used to argue against monolithic programs. So I dispute that the goals/approaches are clearly documented on this page. I fully agree with tool_xxx_is_missing_critical_feature_yyy_what_can_i_do I also think telling users to go away is counter productive. One management technique that I have learned (I think in the army) is that some talks with people should be done one on one and not as a dressing down in public! Steve Meier On Mon, 2009-01-12 at 17:43 -0500, Ales Hvezda wrote: All, Oh no, not again... We have already had this _exact_ same endless discussion a couple of months ago. People, please go back into the archives and re-read the previous discussion and take all follow up offline. Please? [ snip everything cause it has been hashed out before ] Joerg, Posting the same complaints again and again, does *not* help your cause and will not generate any action/attention/sympathy. Again, please read and act upon the advice given at: http://geda.seul.org/wiki/geda:faq#tool_xxx_is_missing_critical_feature_yyy_what_can_i_do In particular bullets one and three. I think that all developer goodwill and kindness (bullet two) has already been spent in full. In the end, my final recommendation is that you go out and purchase a commercial EDA package that meets all of _your_ needs. This project is really not for people who are unwilling/unable to accept the published goals/approach [1]. Let's all try very hard to avoid such repeat threads in the future. Thank you, -Ales [1] The gEDA project's goals/approach are clearly documented at: http://geda.seul.org/wiki/geda:faq Please read it in full. If you do not agree with these goals, please find some other mailing lists to inhabit. Thank you. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Who is evil?
I would caution. That labeling of a company as evil just because they are offering use of proprietary tools, will probably turn off a lot of companies that you would like to sponsor geda. Show the corporate world that geda is more flexible, a strong supportive user base, support for simulation and integrates well with established tools. Don't expect to win the hearts and dollars of corporations on some sort of ethical argument that is counter intuitive to most us companies marketing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is gnetman available for download anywhere?
The stock libgeda supports net type or bus type pins. I would just make it an option when editing a pin. Make the default type a net type. Current gschem behavior of a bus type not being able to connect to a net is fine thanks, Steve Meier On Fri, 2009-01-02 at 20:48 +, Peter Clifton wrote: On Fri, 2008-12-26 at 09:10 -0800, steve meier wrote: one last thought. If you want to use hierarchical buses then you have to be able to set a symbols pin type to being a bus type. The one mod that I would love to see in gschem is the ability to set the pin type when editing a pin. I have done this for a couple of versions of gschem in the past. You can also use a text editor to set the pin type in the symbol file. I'll try to get this fixed for the next development snapshot. I've got some code which fixes up the drawing of bus type pins to make them, and their cues fatter. There is also the updated logic to allow gschem to recognise the connection between a bus pin and a bus, disallowing net-bus pin connections etc.. I'm almost done with the above changes, however I'm not so sure where to stash the option for switching a pin to / from being a bus pin. Since the stock gnetlist doesn't grok buses, I don't want to make it _too_ obvious, so that we don't mislead users into thinking they will get connectivity by this method. Shortcut key? Menu item? Context (popup / right click) menu item? One other idea I was toying with was the possibility of extending / specialising the multi-attribute editor to edit more properties of an object. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is gnetman available for download anywhere?
I am publishing this with a fair amount of trepidation, as I am going to be off net starting in a couple of hours for the next week and a half. And will not be available to support any issues. The only reason to use my custom netlister is if you want hierarchical buses. Please review the documentation in mra_netlist_new/doc/Netlist Users Guide V1.odt (open office) I have moved a copy of my custom netlister and the required library onto my web server. My fear is that without the latest documentation which isn't available until after I get back home it is going to be challenging to use. however, you will need http://www.alchemyresearch.com/libakeda_20081125.zip http://www.alchemyresearch.com/mra_netlist_new_20081125.zip build and install these for me the installation ends up in /usr/local/share/akeda You will probably have to copy your symbols into /usr/local/share/AKEDA/sym to run the netlister mra_netlist -g PCB -l akeda-flat-netlist -o file.net top.sch one bug I have is that it currently supports only one top level schematic. So to build multi-page schematics I start with a top level schematic and use hierarchical symbols in it (flat ones can be used as well) Short explanation. the netlister reads in the schematic pages and symbols and builds up the data structure. But makes no attempt to do anything with it unless a second script is run. The second script is the akeda-flat-netlist.scm which does the work of flattening the schematics and symbols into a single potentially massive undrawable page. Then the output script is run This currently supports PCB and PADS netlists -g PCB -g pads If you try this out before the end of the first week of january... well you have my best wishes. Steve Meier On Fri, 2008-12-26 at 03:27 -0800, Yamazaki R2 wrote: I can't find it anywhere. I am desperate to get a real hiererchical netlister working with gschem. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Recommendations for laptop?
I have used sony, toshiba, dell, think pads etc. they all seem about equal quality. So have you decided what is important to you such as is light weight and small more or less important then screen size? minimum number of usb ports do you need an rs232 jack? (these are getting harder to find) do you need to support non-usb flash memory (like from your digital camera) other then that get it loaded with dram and disk space. have fun, Steve Meier On Fri, 2008-12-26 at 04:54 -0800, Larry Doolittle wrote: Stuart - On Fri, Dec 26, 2008 at 07:33:13AM -0500, Stuart Brorson wrote: Ordinarily I'd buy a reconditioned IBM Stink Pad from IBM, and then stick Fedora on it. Stink Pads are mechanically robust, and they play with Linux easily. However, IBM has sold the Stink Pad division to China, and I am reluctant to get a Levano because of quality concerns. I have no regrets getting a ThinkPad X40 from eBay for US$400, a few months ago. Maybe a little larger, slower, and less glitzy than a similiarly priced netbook. But a good clear 1024x768 screen, and mechanically robust as you say. The X40 was the last true IBM model, before Lenovo took over. You can find them at 1.2, 1.4, and 1.5 GHz, and with a variety of wireless cards. - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist and hierarchy
kind of in synch with this I have been putting my gnetlist and other netlist notes in order. Due to my own email troubles earlier this year I am longer subscribing to geda-dev, looks like I will have to reconnect to that. Since I am not at home, if you could copy me directly Oliver I would appreciate it. Thanks, Steve Meier On Fri, 2008-12-19 at 18:09 +, Peter Clifton wrote: On Fri, 2008-12-19 at 18:13 +0100, Oliver Florian wrote: Hi, @Ales: Thanks for the statement, alone the certainty helped me a lot, really. @Steve: Thank you very much for your interest (sorry for my late reply, I've been experiencing trouble with my email account). I am still very interested in a non standard netlister, although I already solved my problem another way (see below). The whole matter is a bit tricky to describe, since I'm not dealing with normal electric circuits, but I am using gEDA for a special task roughly located in the area of dataflow programming. I think it's best I mail you some more details, because I don't want to annoy the whole mailing list here. Sounds interesting, please do send the details. Perhaps to the geda-dev mailing list, where I'm sure the developers will at least be curious to see how you're using the software. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org
Me thinks the odds of an ice storm in both Texas and New Hampshire concurrently is very low On Thu, 2008-12-18 at 12:43 -0500, DJ Delorie wrote: Thanks to John Griessen, gedasymbols.org now has a second server. Normally, both servers are used, but in the case of yet another outage at my house, John's server should take over. DNS should fail over to my DNS secondary, which is at my ISP. Note that cvs commits trigger updates, so no extra actions or delays are required when you make changes to your gedasymbols area. DJ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
Steve, Sure sounds like a good starting point. Steve M. On Wed, 2008-12-17 at 00:23 -0500, Steve Morss wrote: A year or two ago, I made a footprint replacement program which worked very well for me (I used it to swap out a few hundred parts with about 50 different footprints). It worked like this ... It assumed the description was the file name. Then it looked at the parts in the pcb file, compared them to the new parts (with the same name), and put the new footprints on the same side of the board with the same rotation. It tried not to make too many assumptions about the relationship between the old and new parts. The origins needed to be in the same relative spots and the pin numbering order couldn't change (too much). For each footprint, it tried rotations of 0, 90,180, 270 degrees, and if all the pins ended up in the same quadrants, it assumed the rotation was good and used it. If it couldn't find a rotation, it told you so. This algorithm allows silkscreens to change aribitrarily and pad sizes and shapes to change arbitrarily. If things go well, it writes a new pcb file with all the footprints updated. It was all very scriptable - I ran it as part of a Makefile. It's all written in Perl. If you are interested, I could pull together a set of files and post them. Steve DJ Delorie wrote: What are the most common reasons that you need to change land patterns? Silkscreen changes Thermal pads - mostly for making paste masks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
another good starting point. and the added fun of competing implementations. On Tue, 2008-12-16 at 23:20 -0800, Dean Ferreyra wrote: gene wrote: That is, modify a footprint in a library then have it get updated on all instances on the board - or at least be able to update a single instance. Is this possible? I found some older list messages addressing this and the answer was no. Maybe the situation has improved? I wrote a plug-in for this a while back. I can't make any promises, but maybe you can give it a try and see if it works for you: http://www.bourbonstreetsoftware.com/PCBFootprintUpdatePlugIn.html (You can browse the sources here: http://www.bourbonstreetsoftware.com/viewvc/bin/cgi/viewvc.cgi/projects/pcb/plug-ins/footprint-update/ .) Dean gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org - site down?
Yes. The weight of the ice on top of the wire was sufficient to twist the wire upside-down. No wonder I had to flip the symbols I just down loaded ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
I think, and there are those who wish I wouldn't, that a script could be written which would search through a pcb file and find a land patterns and the replace the land pattern with a new one.. make sure you get the rotations and put the new symbol on the correct side of the board. This is probably a day project for some one who knows how to write scripts (pick your language). If you don't this would be a good excuse to learn to write some basic code and then write the script. But if you are DJ you probably it almost done in the time it took me to write this email. If DJ has power. Seriously, this would be a good beginner project. Steve Meier On Tue, 2008-12-16 at 21:38 -0500, gene wrote: That is, modify a footprint in a library then have it get updated on all instances on the board - or at least be able to update a single instance. Is this possible? I found some older list messages addressing this and the answer was no. Maybe the situation has improved? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
For the advanced student do it as a plugin to pcb. On Tue, 2008-12-16 at 21:40 -0500, DJ Delorie wrote: That is, modify a footprint in a library then have it get updated on all instances on the board - or at least be able to update a single instance. Is this possible? I found some older list messages addressing this and the answer was no. Maybe the situation has improved? No automatic way. Manual way: load the new footprint into the buffer (through the library or file-load element). Shift-click it over the old element, and it replaces the old element while retaining all its attributes (value, refdes, etc). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
I was thinking that the pcb file format does have a specific place components are found (in the pcb file). So a string comparison of the old string against the searched for string should work. Given that we found a match. Can we align the old land pattern in terms of x-y translation and rotation? I think this is also do-able. It does assume you have a copy of the old land pattern. Now can we align in terms of translation and rotation the new land pattern to the old land pattern? This might be the tricky part, if this is just a geometry change in terms of pad size it might not be to bad. What if, a exchanging a land patterns because we got the pin order wrong. I think just do it (perhaps an option to let the user choose between an assumption of device centering or of a designated pad as the center) and then let the drc tell us our nets are shorted. This project is getting more interesting. Steve M ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
Just to put it on the screen an example land pattern. Element(0x00 Surface Mount Chip Resistor 0603 R0 0 0 -31 -82 2 100 0x00) ( Pad(-2 0 2 0 39 30 50 pad 1 1 0x0100) Pad(65 0 69 0 39 30 50 pad 2 2 0x0100) ElementLine(-21 -35 87 -35 5) ElementLine( 87 -35 87 35 5) ElementLine( 87 35 -21 35 5) ElementLine(-21 35 -21 -35 5) ) The Element tag has three strings if I have the old land pattern I think that I can reasonably presume that if I find a land pattern in a pcb file that matches the first string Surface Mount Chip Resistor 0603 that they are the same. I could go a step further or two. Same number of pins? same number of pads. same pin and pad pin numbers? A key point is that you have to have the old land pattern. Also by having the old land pattern you know where the land pattern origin is. The origin is 0 0. On Tue, 2008-12-16 at 22:06 -0500, DJ Delorie wrote: So a string comparison of the old string against the searched for string should work. What string? There are three strings stored in elements - value, refdes, and description. None are supposed to *always* include the filename! gsch2pcb happens to use description to store the footprint name, but that's not something pcb enforces. Can we align the old land pattern in terms of x-y translation and rotation? I think this is also do-able. It does assume you have a copy of the old land pattern. The assumptions are: 1. The description field is the footprint name. 2a. The locations of at least two pins don't change. -or- 2b. The location of the mark and at least one pin doesn't change. Be careful about swapping the endpoints of SMT pads, though. Midpoints of SMT pads might be a better choice, but then again, that prevents you from making the pads longer on one side (think extending QFP pads outward). This is what I like about these kinds of projects. There are probably multiple solutions so how to first implement one and then expand it to many and then evaluate the possible solutions for the best one. What if, a exchanging a land patterns because we got the pin order wrong. I think just do it (perhaps an option to let the user choose between an assumption of device centering or of a designated pad as the center) and then let the drc tell us our nets are shorted. user-chosen pins might make sense. Default could be pins 1 and 2, or mark and 1 (mark and 2 if mark overlaps 1). I think we should presume that the two patterns have the same pin numbering scheme. Might make sense to add some rule checking before attempting the swap. Do both the new land pattern and the old have the same pins. Does the new one add/remove pins (not necessarily a problem). As I said more interesting. This is an area that a google summer of fun project might make sense and produce a usable algorithm that could become a plug in. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
A good survey question: What are the most common reasons that you need to change land patterns? Steve Meier On Tue, 2008-12-16 at 22:38 -0500, DJ Delorie wrote: I could go a step further or two. Same number of pins? same number of pads. same pin and pad pin numbers? Each thing that must match is one more thing that you can't change and still update the footprint. A key point is that you have to have the old land pattern. I wouldn't rely on that. I think we should presume that the two patterns have the same pin numbering scheme. I often fiddle with the thermal pads on footprints, replacing one big pad with many smaller ones. Getting these rules right is most of the work in this type of project. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: modify footprint and update layout
The pattern I picked had the wrong dimensions. The pattern I picked had the pin numbers wrong. On Tue, 2008-12-16 at 19:42 -0800, Steve Meier wrote: A good survey question: What are the most common reasons that you need to change land patterns? Steve Meier On Tue, 2008-12-16 at 22:38 -0500, DJ Delorie wrote: I could go a step further or two. Same number of pins? same number of pads. same pin and pad pin numbers? Each thing that must match is one more thing that you can't change and still update the footprint. A key point is that you have to have the old land pattern. I wouldn't rely on that. I think we should presume that the two patterns have the same pin numbering scheme. I often fiddle with the thermal pads on footprints, replacing one big pad with many smaller ones. Getting these rules right is most of the work in this type of project. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gedasymbols.org - site down?
maybe we ought to set up a mirror. Steve Meier On Mon, 2008-12-15 at 19:59 -0500, John Luciani wrote: The Northeast (U.S.) was hit with a major ice storm. IIRC gedasymbols.org is on DJs server which is located in NH. On the news tonight they were saying that some NH customers may not have power for a week or two. (* jcl *) On Mon, Dec 15, 2008 at 7:52 PM, Saritha Kalyanam kalyanamsari...@gmail.com wrote: Is the [1]gedasymbols.org site down? Thanks, Saritha References 1. http://gedasymbols.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Press release: gEDA Project and Linux Fund partner to boost gEDA/PCB usability
Very cool. Is there a list of enhancements to be done as pert of this project? Steve Meier On Sun, 2008-12-14 at 17:23 -0500, Stuart Brorson wrote: Good news for gEDA users! Please read the below press release, of interest to all gEDA users. It has gone out to a variety of EE news sources, as well as mainstream press release sites. Cheers, Stuart December 15th, 2008 gEDA Project and Linux Fund partner to boost gEDA/PCB usability Help bring open source circuit board design into the mainstream. The gEDA Project is pleased to announce that it has partnered with Linux Fund in a fundraising effort targeted to expedite development of gEDA's flagship PCB layout program PCB. Within this partnership, expert gEDA/PCB developer DJ Delorie has agreed to implement a set of enhancements designed to upgrade PCB's usability and utility for electronics designers, making it an attractive open source alternative to commercial PCB design tools. With this project, gEDA/PCB joins the VectorSection DWG interpreter project as part of Linux Fund's growing open engineering and hardware initiative. PCB is a twenty year old application. Originally written in 1990 for the Atari ST, the program was ported to Unix in 1994. Over the years, it has been maintained and extended by a series of developers who have added improvements and new features, including the ability to export Gerber RS-274x files, an autorouter, and a GTK port. Mr Delorie is currently one of the chief developers involved with PCB, having become involved with the project in 2002. DJ Delorie is well known within the open source community as the author of djgpp, a popular port of the gcc compiler to DOS. He is also a long time user of PCB, having used the program to design a net-enabled alarm clock which won second place in Circuit Cellar Magazine's Microchip embedded control design contest in 2007. His commitment to work on PCB usability enhancements in conjunction with funding from the Linux Fund represents a major step forward for the gEDA Project, as well as a welcome boost to the open-hardware movement. gEDA/PCB upgrade work description: * Implement forward annotation using action scripts * GUI modernization * Enhance ability to create and edit arbitrary layer types * Develop a new Footprint Editor * Update Design Rule Checking About the gEDA Project The gEDA Project is a community of open-source developers working on creating tools for electronic design released under the GNU Public License. The project currently offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout. Besides the core design tools, the gEDA Project has gathered a community of other programmers who work on their own tools while sharing the gEDA e-mail lists, administration, and community support. This extended set of electronics design applications has become known as the gEDA Suite. Visit http://geda.seul.org for more information about the gEDA Project. About Linux Fund Linux Fund is a 501(c)(3) non-profit organization that provides financial and supervisory support to the open source software community. Linux Fund raises funds with its line of rewards credit cards and direct donations, and has given over half a million dollars to open source projects since its founding in 1999. Visit http://www.linuxfund.org for more information about Linux Fund and to help support the gEDA/PCB Project. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is it possible to route through ...
Gene, For a 0.8 mm (31.5 mill) pitch device if half the space is for the pad (16 mills) that leaves (15.5 mills) space between the pads. This is plenty of room to put a 6 mill width trace through. For a 0.5 mm (19.7 mill) pitch device if half the space is for the pad (10 mills) that leaves (9.7 mills) space between the pads. This is plenty of room to put a 6 mill width trace through. In fact if you said 6 mills for the trace + 2 mills extra your pad could be 11.7 mills. One thing that concerns me is that this vendor's standard is 6 mills trace width and you are discussing a 0.5 mm pitch device. I would not be comfortable. Have you asked them if they typically build fabs to these dimensions? The issue of dropping the vias through the board is that each vias requires a pad around it. What will be the dimensions of these pads. Are you going to stagger the vias so they don't interfere with each others traces? I am familiar with bga devices with pitches of 1mm and I have squeezed 4 mill pitch traces between rows to escape the device. More typically I use a 4 mill width (now that pcb supports more then 8 layers) Steve Meier On Sun, 2008-12-14 at 21:30 -0500, gene wrote: Steve Meier wrote: Gene, My understanding is that the minimum solder mask is dimension is 5 mills (check with your vendor). So if you have a solder mask cover of 5.5 mills between pad openings then a trace of 4.5 mills or smaller should not be a problem. I have used traces as small as 3 mills. I believe for the copper layers this suggests you should use 0.5 oz copper thickness. Steve Meier I checked a couple of online fab outfits, and found at least one that will do 6 mil trace with 6 mil space. I think 3 mil is going to be a little out of the ordinary. For now, in order to avoid any additional cost, maybe 6/6 is a good size to use for those dense areas. But then again, that means minimum space between pins of 18 mils. That won't fit very well in the .8mm pitch part I described and looks pretty much impossible on 0.50mm pitch part. Maybe the better solution is to run the bus on one side of the card, and drop vias from the other side. It's just going to make a lot of swiss cheese, I think, on the card. I'm open to suggestions :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hanging a jack off the edge
yep. Make the pcb work area larger then the board. add a silk screen around the edge of the board or make a separate board layer and put the outline there. Add a fabrication instruction to make the board to the outline. Steve M. On Fri, 2008-12-12 at 20:08 -0800, David Griffith wrote: Is there some way I can convince PCB to allow me to hang the footprint of a jack off the edge of a board? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist and hierarchy
Oliver, I do have a non-standard netlister designed specifically for hierarchical designs (especially for using buses to connect symbols together). I have done designs which have used multiple instances of hierarchical symbols. But I am still not sure what your question is. Could you post or send me an example design? Along with comments about what your desired behavior is? Steve Meier On Sun, 2008-12-07 at 02:26 +0100, Oliver Florian wrote: Hi everybody, I'm currently working on a netlister backend and I am desperately looking for a solution regarding a problem with hierarchical structure: Problem: Within my scheme backend, I'd like to get the virtual component representing the sub sheet (the one with the source attribute set), more precisely it's about the attributes of that subsheet component, but without disabling the hierarchy traversal. As you might know, the netlister gets all components in a flat structure, with a reference to the hierarchical structure merely present in the package and net names. Details: There are two reasons for all this: First, I generically need to set attributes that apply tho the whole sub sheet. And second, I need to be able to use sub sheets multiple times inside the higher level schematic, but inside my netlist-file there is declarative code which is required exactly once for each sub sheet, no matter how many instantiations of it exist. Obviously, solving the more generic problem would solve this one as well, since I could simply check for matching source attributes to detect different instantiations of the same sub sheet. Does anyone know how to accomplish this (if possible at all)? Or does anyone have a non-stantdard version of the netlister that could be of help in this regard? I am aware of the gnetlistrc option hierarchy_traversal, the problem is I need both the hierarchy traversal _and_ getting a hold of the subsheet symbols. All I read so far seems to mean there is no way to do that (although I haven't found a discussion on the very same problem, so far). Any help would be greatly appreciated, thanks for your attention so far. Oliver ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (no subject)
No no Peter that would let you off far to easy. Your punishment for this infraction is the next 100 pieces of spam that hit your in-box. Would should have occurred by right . now. On Tue, 2008-12-02 at 12:27 +, Peter Clifton wrote: On Mon, 2008-12-01 at 21:25 -0500, Dave McGuire wrote: On Dec 1, 2008, at 4:21 PM, Ethan Swint wrote: [snip] The header isn't displayed by default in many email clients. To view the header in Thunderbird, press Control-U. Even then, that string isn't the most obvious. To anyone who knows anything about email, it's quite obvious. And anyone who doesn't know at least that much about email has absolutely no business USING email. Knowing that email has headers, and knowing that a mailing list might add a header detaining how to unsubscribe are two different things. In spite of not knowing this, I've happily managed to subscribe / unsubscribe to countless mailing lists without anyone's help (and sort into folders using sieve, based on mail headers). But, anyway - I didn't know that one existed... I guess I should be banned from using email. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (no subject)
I tried, but the brake lever is stuck! On Mon, 2008-12-01 at 21:30 -0500, DJ Delorie wrote: Self-sufficiency has quite obviously gone out of style. Stop the world, I want to get off. See, now, if you were thinking clearly you'd want to stop the world so everyone *else* could get off. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: (no subject)
I am also sure, that somewhere within the windows vista operating system is a universal reset. Where is that button?. There might be a similar system call within linux but DJ is to worried about his clock to tell me the key to the obfuscated code. On Mon, 2008-12-01 at 18:41 -0800, Steve Meier wrote: I tried, but the brake lever is stuck! On Mon, 2008-12-01 at 21:30 -0500, DJ Delorie wrote: Self-sufficiency has quite obviously gone out of style. Stop the world, I want to get off. See, now, if you were thinking clearly you'd want to stop the world so everyone *else* could get off. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some kind of library manager and hierarchical netlisting
Peter, I believe that gnetlist takes in a hierarchical series of schematics and flattens the schematics into a flat netlist that may then be exported into a number of flat formats. In other words the net has been flattened before reaching the backend. Hierarchical information is retained in reference designators and in net names. It would be a non-simple task to reconvert the hierarchical information in the reference designators and nets back into a hierarchical format. Steve Meier On Wed, 2008-11-19 at 10:32 +, Peter Clifton wrote: On Wed, 2008-11-19 at 10:23 +, r wrote: Hi, I hit exactly same issues last time I tried to use gschem/gnetlist. The flow simply doesn't work with hierarchical designs (and yes, there is no notion of a design library in geda). That simply is not true. The netlister _does_ work with hierarchical designs, but typically, our back-ends target a flat output, such as for PCB. There are symbol and source libraries (symbols and underlying schematics). Granted, we probably could do with adding some polish, but depending on what you're wanting as your final output, you can do hierarchical designs. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some kind of library manager and hierarchical netlisting
Yamazaki, I have done a fair amount of work on hierarchical netlisting. However, I run my own customized versions of libgeda and gnetlist. In my version, each page is netlisted separately and thus a back end could be written to retain the hierarchical information. Steve Meier On Tue, 2008-11-18 at 15:27 -0800, Yamazaki R2 wrote: Has anybody made some kind of library manager like the cadence library manager in icfb to manage schematics and symbols? Something where in the schematic editor I can type in a library name and cell name it and automatically instantiates the symbol/schematic combo in the hierarchy? Also, I know by default the gnetlist program does not contain a scheme that can do hierarchical netlisting, but has anybody in the community made a scheme that can do hierarchical netlisting? Thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, how to remove mm garbage (very short lines)?
The Pads ASCII format uses a base unit of 0.0002624671916 inches which is 1.054 nM Converting it to metric causes an error of about 0.5 nM The PCB base unit is 0.1 inches Converting it to metric causes an error of 19.7 nM All I can figure out about why pads uses that weird number is that multiplying it by 38100 converts the base unit to mills Multiplying it by 9678 converts the base to 10 microns with an error of .6 nM So making the base smaller will reduce error (no surprise) the question is what is a tolerable error? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, how to remove mm garbage (very short lines)?
I think the base should be one Angstrom for two reasons. 1) that it would be 10x the resolution of the pads. 2) According to wikipedia (with the ångström being officially discouraged by both the International Committee for Weights and Measures and the American National Standard for Metric Practice). Steve Meier On Wed, 2008-11-19 at 10:22 -0800, Steve Meier wrote: The Pads ASCII format uses a base unit of 0.0002624671916 inches which is 1.054 nM Converting it to metric causes an error of about 0.5 nM The PCB base unit is 0.1 inches Converting it to metric causes an error of 19.7 nM All I can figure out about why pads uses that weird number is that multiplying it by 38100 converts the base unit to mills Multiplying it by 9678 converts the base to 10 microns with an error of .6 nM So making the base smaller will reduce error (no surprise) the question is what is a tolerable error? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, how to remove mm garbage (very short lines)?
1 in = 25.3972 mm not exactly 25.4 but close enough for layout work if you use high enough precision. 25.4 to 1 might not be close enough if you are trying to put a satellite in orbit around mars. Steve M. On Wed, 2008-11-19 at 18:58 -0700, John Doty wrote: On Nov 19, 2008, at 4:08 PM, Peter Clifton wrote: On Wed, 2008-11-19 at 15:44 -0700, John Doty wrote: If you insist on no artifacts, it's zero. If you round imperial units to the nearest 0.01 mil, you have no additional roundoff error if your fundamental unit is 1 nm, because 0.01 mil is *exactly* (by definition) 254 nm. Good point... meaning it would be sensible to move towards some kind of metric internal units, or an intrinsic coordinate system with units in metric being given the divisor of 254 * 10^n. It's much harder to go the other way with a humanly comprehensible rounding because of the factor of 127 in the definition of the inch. I get that 127 * 2 = 254.. which definition of the inch mentions 127 explicitly though? I have multiple reference books that state 2.54 cm = 1 inch exactly. Presumably there's some SI or NIST definition. 2^32 nm is about 4.3 meters, large enough for any PCB I've ever seen. 2^64 nm is about 0.12 astronomical unit ;-) Well.. I can't recall if we use signed or unsigned numbers throughout, so we might end up limited at half those. If it's signed, you can go 2.1 m either way, so it's the same. Aren't 64 bit integers going to be slow on a 32bit CPU? How slow. What fraction of computation is arithmetic in world coordinates? Practicalities of changing: 1. Change internal units: ought not to be _that_ hard since DJ nicely abstracted things away when he refactored to introduce the HID (IIRC). Make loading / saving convert to the old units, (rounded to integers). 2. Add unit specifiers to file-format, so users could, if they want, write out coordinates such as: 5mm, 10mm or 5 mm, 10 mm. from their footprint-generation scripts. Save the files out with native units, e.g. 123456000 nm Perhaps, for optimal flare, we could make it more human readable, by writing out something decimalised, like: 123.456 mm (*) If the coordinates for a point happened to be a convenient decimal fraction of an inch (requiring less decimal places / significant figures than the metric representation), then we could choose to emit in mils, or inches etc.. * (Taking care not to loose precision if we were to read it back via a floating point number). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, how to remove mm garbage (very short lines)?
Interesting. OK I think for PCB purposes 1 inch is exactly 2.54 cm by definition. 1959 the national standards laboratories of the English-speaking nations agreed to standardize the relation between the yard and the meter For geodetic data here in the US the traditional value of 1 yard = 3600/3937 meter or 1 yard = 0.914 401 8288 meter Which works out to be 1 in = 0.025400051 m Steve Meier http://www.wsdot.wa.gov/Reference/metrics/foottometer.htm On Wed, 2008-11-19 at 19:45 -0700, John Doty wrote: On Nov 19, 2008, at 7:21 PM, Steve Meier wrote: 1 in = 25.3972 mm not exactly 25.4 but close enough for layout work if you use high enough precision. Where'd you get that? I have multiple references that say it's 25.4 *exactly*. To even be able to measure distances of order 1 inch at the level of precision implied by your statement may be impossible. You're talking subatomic dimensions here... John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Want to Use TI's symbols, footprints
I am pretty sure the answer is yes Steve Meier On Thu, 2008-11-13 at 13:45 -0500, Ethan Swint wrote: Duncan Drennan wrote: How about making use of the IPC-7351 footprint definitions instead? You can grab the free PCB Matrix land pattern viewer and calculator here, http://www.pcbmatrix.com/Downloads/LPSoftware.asp. That footprint would be a SOT95P280X145-5M (most version). I've attached that footprint. Thanks for the footprint definition. The calculator, unfortunately, is Windoze only, and Wine is missing the .net framework. Curiosity question: do the TI footprints that involve thermal pads fall within the IPC definitions? -Ethan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using KiCAD netlist for PCB
Can you attach an example KiCAD netlist? Steve Meier On Thu, 2008-11-13 at 22:01 -0200, Raphael Derosso Pereira wrote: Is it possible at least? Then I could finish schematics in KiCAD and begin layout on PCB. -- Raphael Derosso Pereira Engenheiro de Computação icq: 4517421 msn: [EMAIL PROTECTED] Skype: rderossopereira References 1. mailto:[EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter board, with less ground planes :-)
I can't speak about all regions of the country let alone the world. but yes ask ask ask why do you do that if you use that tool what are the requirements I did ask today, uhm looking at DJ's clock ok yesterday. The assembly shop had a tool that would look around under the bga... what clearances does that tool require? (they fessed up to breaking a few probes early on) how tightly can I pack devices? does putting smt caps under a bga degrade the xray imaging? We as engineers need to understand these issue from a manufacturability view point. We as geda need to understand these issues so that our tools can be developed to meet the requirements of manufacturers. And our tools need to be very very very extensible so that we can describe every thing from a high school science project to a 5 mill pitch flip chip on a flex circuit (rotated 0.63 radians). On Sat, 2008-11-01 at 00:11 -0400, Dave McGuire wrote: On Oct 31, 2008, at 10:02 PM, Bob Paddock wrote: Ask the person on the line what you can do to improve your board from his/her perspective. If you don't ask the people doing the work (not the front end customer service/sales people who aren't doing the work) you may never hear any complaints from anyone, because of the Customer is always right policy. Well, at least ONE industry still has such a policy. ;) -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter board, with less ground planes :-)
If having to switch between nozzles is a significant issue then there is room for a new pick and place equipment company that builds a multi-nozzle tool. In reality, I doubt that it has much of an effect on cost. I wonder how the throughput of the pick and place tool compares to the throughput of the reflow oven? or wash or final inspection? Steve Meier On Fri, 2008-10-31 at 20:31 -0400, Bob Paddock wrote: On Friday 31 October 2008 03:43:20 pm Joerg wrote: Much better. If you want to be extra good provide another 0.1uF parallel to the AVDD caps, close to pin 3. C13 in your channel.sch file. However, 10uF cermamics in SMT are already quite good these days, and cheap. If you can get C13 closer to pin 3 that would also help. A bypass-capacitor dialogue peels back the layers, Part 1 http://www.planetanalog.com/article/printableArticle.jhtml?articleID=207602816printable=true Interesting article that says it is better to use bypass caps in different size packages due to ESL effects. Part 2: http://www.planetanalog.com/article/printableArticle.jhtml?articleID=208402807printable=true ... David: Follow the currents. There is always a loop for current, there are always fringe currents inside the ground plane, and voltage drops associated with those currents. The cuts prevent the currents from mingling so they could no longer couple directly from Input A to Input B (or the reverse). Tamara: So this was an example of a ground plane gone wrong. The ground plane with cuts in it actually performed better. David: Yeah, most people believe that providing a low-impedance connection to ground (like a plane) is enough. Sometimes that is true, but it's too one sided. If you need really high isolation, you need to follow and control the currents around the entire loop. ... Part 3: http://www.planetanalog.com/article/printableArticle.jhtml?articleID=209600453printable=true Do a search for Bypass on Planet Analog for related articles. Doesn't look like they used PCB in the screen shots. ;-) Might want to rotate C11 and squeeze it in between R18/C12 so it's closer to pin 4. When Squeezing parts between things, consider what happens at the assembly stage. For example you put a tiny 0402 0.1 cap between to comparatively large parts like a 1206 resistor and a large tantalum capacitor. This could create a problem with the PickPlace machine where your board might need two passes on the machine, increasing your assembly charges. The 0402 cap will need a tiny nozzle to place it and fit between the larger parts, while the larger parts need larger nozzle due to the part mass. If the 0402 part is on the outside of the larger parts then it is possible that the larger nozzle could be used for all operations in that area, this saves time hence cost. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter board, with less ground planes :-)
Inspection is moving to aoi automated optical inspection and flying probe test. Speaking of which the Flying probe test needs locations of pads and vias and are used to the pad's ascii style file. I have actually made a lot of progress importing a pads ascii file into pcb and once I can read the entire file (i am down to the netlist) I plan on working on a conversion script from pcb to pad's just to support the flying probe. I was visiting an assembly shop checking to see if they can load an 8 mill pitch flip chip for me today. I do like looking at their toys. Steve M. On Fri, 2008-10-31 at 20:58 -0400, Bob Paddock wrote: On Friday 31 October 2008 08:40:44 pm Steve Meier wrote: If having to switch between nozzles is a significant issue then there is room for a new pick and place equipment company that builds a multi-nozzle tool. They do exist of course, but there maybe other reasons why they can't be used in a particular machine load. In reality, I doubt that it has much of an effect on cost. I have known it to cause a board to require two complete passes through the machine, or the worse case of two different machines. One pass for the big stuff and one pass for the small stuff. I wonder how the throughput of the pick and place tool compares to the throughput of the reflow oven? or wash or final inspection? Depends on the equipment, your process set up, and the board. 1000 part board is going to take more time to load and inspect than a 100 part board, while reflow and wash hold the time more or less constant for either board. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: powermeter board, with less ground planes :-)
It isn't your clock that is pulling all that power is it? Steve M. On Fri, 2008-10-31 at 22:45 -0400, DJ Delorie wrote: At the end of the day the only thing that counts is whether it's good enough and it looks like DJ's board should perform pretty well now. And yet I keep improving it anyway. http://www.delorie.com/electronics/powermeter/bypass-2.png The red ground planes on the left side perhaps aren't needed, but they make it easy to connect all those parts, and every bit of unetched copper saves the environment! ;-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Ok ok ok go to my home page and look for links to hs table of contents and hs section 1 through 4 http://www.alchemyresearch.com/ Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
No the first attempt was a cut and paste that didn't bring the url with it though an html filter would have removed it. The second and third attempts I was responding only too myself. Good thing too as I was getting frustrated with how my email tool automatically breaks lines into pieces. And the urls are convoluted. Steve Meier On Thu, 2008-10-30 at 19:14 -0700, Steven Michalske wrote: Were you trying to format them with HTML? I bet the HTML filters on the mailing list were cutting out the links. On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote: Steve, I don't see these other attempts. Eric Winsor Steve Meier wrote: Dave, No I struggled three times to get usable url's so go down a couple more of my attempts and then you will have to take the line breaks out of the ultra long url but you can get there. Steve Meier On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote: I don't see any URLs in there.. -Dave On Oct 29, 2008, at 6:08 PM, Steve Meier wrote: I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On Tue, 2008-10-28 at 20:47 -0400, DJ Delorie wrote: Joerg [EMAIL PROTECTED] writes: By now I'd say Prehistoric Digital Assistant. The only guy I know who actually still uses one is our pastor. I have one I use every day, but it's in my watch. So that watch isn't on a wrist band it is on an adjustable crane hook. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I went looking to see if the Analog Device book was available electronically. Here are the links. Steve Meier High Speed System Applications Table of Contents High Speed System Applications Section 1: High Speed Data Conversion Overview High Speed System Applications Section 2: Optimizing Data Converter Interfaces High Speed System Applications Section 3: DAC, DDS, PLL's, and Clock Distribution High Speed System Applications Section 4: PC Board Layout and Design Tools On Tue, 2008-10-28 at 13:44 -0700, Steve Meier wrote: I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Size of symbols
I like a hierarchical schematic where I have a top.sch which has symbols for each of the major subsections and I use buses for most digital signal paths and nets for the analog paths to interconnect these symbols. When you have designs with a thousand components on it I don't care how small your symbols are or how big your printer is it ain't readable. Steve Meier On Wed, 2008-10-29 at 18:22 -0400, Dave McGuire wrote: On Oct 29, 2008, at 5:33 PM, John Doty wrote: Should I adjust the size of the symbols or the size of title-B.sym? What is the correct way and how do I do that? I would adjust the size of the symbols. The standard symbols seem a bit too big for me as well. That's not the paradigm. The way gEDA works is that you keep the symbol size constant in gEDA's arbitrary units, and make the extent of your page what you want to shrink them to the size you want. I personally find title-B about right for letter or A4 paper with the existing symbols. I like modules I can comprehend, not spaghetti going all over the place. I also don't want to give the bifocals too much of a workout ;-) Note that you don't have to use a titleblock at all. Some of my collaborators just put in cvstitleblock-1.sym with no frame, so the schematic just fills whatever page it's printed on. I rather despise the new-fangled plop a component down and attach netnames to each of the pins, with no lines going anywhere methodology, if that's what you meant by your spaghetti reference. ;) What I like to do is have large schematics with small symbols, with a title block, and I print them usually at 11x17. Would it be reasonable to simply use a LARGE title block (say, E size) and scale it to fit the page on the way out to the printer? -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I won't argue this point. I will refer every one to an Analog Device publication High Speed System Applications copyright 2006 ISBN-10: 1-56619-909-3 or ISBN-13: 978-1-56619-909-4 In particular if you get a copy of this book (and they gave me mine) look at pages 4.15 and 4.16 There AD recommends connecting both of the A/D grounds digital and analog to the analog ground plane this is because it causes less problems for the relatively small amount of digital return current to be returned through the analog ground than it would to connect the converter to the much noisy digital ground. There is a lot more talked about then just that one blurb. Steve Meier On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote: Stefan Salewski wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
yes it helps immensely to have a low pass filter issolating a device from the power planes. Steve Meier On Tue, 2008-10-28 at 14:49 -0400, DJ Delorie wrote: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. What about high precision ADCs? I'm working on a design using ADE7753 power monitor chips (16-bit ADCs) , and their own app note (AN564) shows a ferrite isolating analog ground, and a 10R resistor isolating AVdd. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
Nearly impossible? I disagree here it is standard practice. Analog signals come in and go out the left side of the board and digital is in the center to the right side. Top analog is separated from the bottom analog. Here is the deal. We start with a signal less the one milli volt and we increase it over 1000 times. Any noise that crosses over from the digital into the analog gets multiplied up by that gain as well. Steve Meier On Tue, 2008-10-28 at 15:02 -0400, Stuart Brorson wrote: Sometimes it is necessary/recommended to partition (separate) power or ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in http://focus.ti.com/lit/ug/slwu028c/slwu028c.pdf We can do this in pcb program with (adjoining) polygons. Disadvantage is, that if we change the size of one of the polygons we have to manually adjust the other sizes. A other method may be so divide a large polygon by copper clearing traces (with trace width zero). This is related to my question from http://archives.seul.org/geda/user/Sep-2008/msg00387.html but not identical. What is the best way to handle this? I can't speak to that but just one word of caution: In my 20+ years in engineering I have yet to see one case where splitting a ground plane under high-speed ADCs has worked. Regardless of what application notes say. Usually it didn't work, lots of noise. Or it kind of worked but fell apart the instant somebody whipped out a GSM cell phone or BlackBerry. Myself, I never spilt a ground place. OTOH the industry practice of splitting planes is providing part of my income :-) The only time I split is where required for safety, for example patient isolation per 60601 (ECG, ultrasound etc.). I gotta agree strongly with Joerg. ALthough many app notes recommend a split ground plane for mixed signal designs, in the real world it's next to impossible to split the plane properly. That is, with signals (both digital and analog) running all over your board, power, etc., it's almost impossible to gerrymander your AGND and DGND planes to follow their respective signal traces and feeds. Therefore, the folks at National Semiconductor push the idea that you place analog and digital components as far away from one anther as possible on your board. Also, keep analog and digital signal tracks as separated as possible. But use a *single* solid ground plane everywhere for the best noise performance. I've used this advice in practice, and have had no problems (at least with radiation and noise). Here are some app notes discussing this in greater detail: http://www.hottconsultants.com/techtips/split-gnd-plane.html http://www.national.com/nationaledge/nov04/adc_article.html Cheers, Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: On/Off sheet nets in multi-page schematic
For non-hierarchical schematics all nets that have the same net name attributes will be connected. Steve Meier On Tue, 2008-10-28 at 18:13 -0400, Rob Butts wrote: I have a multi-page schematic. I named the schematic according to the gschem guidelines name_pg#.sch. If I want to have a net go to multiple components on multiple pages and be recognized by gsch2pcb can I use the in/out symbols in input/output (generic) menu? Can I name the nets such that the netlister will associate nets named the same but on different pages as the same net? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb, howto partition power planes?
On the issue of powering boards I have been playing with some really neat programmable power supply controllers (surface mount chip) that support power supply modules. Prices of the modules seem to be comparable to the prices of the individual components one would need to build various forms of switching power supplies. The controllers set the duty cycle, phase and frequency of the switching power supplies. This makes it possible to insure that two switchers are switching out of phase with each other. Other parameters which are controlled are delays from power up and rate of power up. So one other trick I use is to isolate each power supply from the rest of the board with a jumper (large diameter holes to support a fat wire). Then when we first turn on the board, we program the power supplies check out their voltages, ringing etc and then we connect them via the jumper to the rest of the board. Steve Meier On Mon, 2008-10-27 at 14:43 -0700, Steve Meier wrote: I agree with Niel, I separate my ground planes with a symbol for a power inductor. I do this at the schematic level and then I read the layout suggestions typically provided by the A/D data sheet on where to connect the planes. For the fab I put in the power inductor foot print. You can then use the power inductor or not. You can leave it open or you can short it. I also do similar activities for power supplies separating the board power from board sections. Makes it very easy to debug the board from one section to the next. Steve Meier On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan wrote: I typically deal with this by separating the planes at the schematic level using a bead-core inductor. Yes, I also have GND and AGND in my schematics. Don't put inductors between ground planes, connect them at a star point. If you are going to use inductors then have them on the power side, not between grounds. How do I best divide a copper area (physically) into subsections with complicated shape/outline. Is there a good way to do this with PCB? It would be relatively easy if planes could be handled as negatives, i.e. everything you see is NOT there. Then it is just a matter of moving a line. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: A few questions about gschem, gnetlist, and gspiceui/ngspice
the gnetlist option -g tells genlist what backend file to use. -g spice uses the file gnet-spice.scm on my machine it is found in /usr/local/share/gEDA/scheme it is also found in the gnetlist source code in the scheme directory Steve Meier On Thu, 2008-10-23 at 11:17 -0700, Yamazaki R2 wrote: Hi all, Let me just say that the gEDA suite is pretty robust for being an open source project. For the most part I am happy with it and really appreciate the work that's been put into this project. It's great EDA option for the hobbyist as well as the professional. Now, I have a few questions/issues that I can hopefully get cleared up: 1. The first thing I want to understand how the gnetlist scheme works for the spice scheme (gnetlist -g spice). When I run this command, what scheme backend files are processed? Only gnet-spice.scm? Or is any other scheme processed along with it? The reason why I ask is because when I take a look at gnet-spice.scm it seems to be getting some variables from somewhere else, as in the file doesnt seem self-contained. The reason why I ask is because I was interested in editing the way the netlister works. I created a 3 terminal nmos and pmos symbol and I want to either hardcore a implicit bulk connection into the netlister scheme or create a symbol attribute that specifies the bulk connection in it, maybe using the net= attribute. When looking at the gnet-spice.scm file, it doesnt show where its getting the number of pins for mosfet devices. The way I was going to go about it was change the number of pins to 3, then print the last net (the bulk) as a netname thats hardcored. 2. I'm having a few issues with gschem. As of the current version, is there a way make filled shapes for symbols that aren't squares/circles? Such as a filled triangle? If not, does any development version have this feature? Another issues/annoyance I'm having with gschem is that the graphical interface inside the schematic is kinda buggy. For example, if I route a net, then delete it, the grid dots don't reappear until I either move the viewing plane or zoom in/out. Is this how it's suppose to work or do I not have my graphics library set up right? Another issue with gschem, is there planned support to actual font rendering at some date rather than each letter being it's own symbol? The reason I ask is because the way it's setup right now causes the fonts too look garbled/unreadable if you're not zoomed really far in. 3. In GSspiceUI, why don't transistors show up in the device list? Do I not have it setup right or is this intentional? Also, why is the option to probe current grayed out when I choose ngspice as the simulation engine? Also, what is the proper probe syntax in ngspice to probe drain/source/gate current in a mosfet? Also collector/emitter/base current in a bipolar? Another (I think) bug in GspiceUI is the fact that it rounds the output voltages/current too much where when you plot it in gwave the granularity is bad. For example It's impossible to graph voltages in the 10s of millivolts because it sounds lots of steps as the same number. Try an input of a 5mVpp sine wave then plot it in gwave and see what I mean. 4. Speaking of gwave, how do I add the voltage/current/time/frequency access to the plots? What about grid lines? Thanks all ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: I hate footprints
Well, there is a fair amount of standardization. Far from perfect but some exits. Devices which use JEDEC packages seem pretty good, few exceptions where you have to watch out for pin number. But JEDEC doesn't cover every available package. I have been working on a spread sheet where I try to capture all of this. My spread sheet is available upon request. Steve Meier On Thu, 2008-07-31 at 18:29 +0200, Philipp Klaus Krause wrote: It seems the only way to deal with them is to create each footprint from scratch eachtime I have to use one. Nearly eachtime I try to use an existing footprint things turn out wrong. There seems to be nearly no standardization in these things. Each chip manufacturer gives them a different name, pcb uses yet another one (if a footprint exits). Different manufacturers call different sizes by the same name. You never know how wide something calles SOP really is etc. So for my latest board I needed something called TSOP-28 in the datasheet. I found something by the same name in pcb. I carefully checked dimensions. They matched. I created a geda symbol. Today I got the chips and started soldering. Then I noticed something seemed wrong. The manufacturer had used a different pin numbering. Why can't manufacturers just provide footprint and symbol in some standard format that all programs could import? I feel like I spend a large part of the time it takes to design a pcb drawing symbols, footprints, etc. Philipp ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Success with gEDA tools...
Reversed polarized cap? Those ones are easy to find upon power up :) I don't think it is sufficient to rely upon the silk screen to provide assembly instructions. For cases like this you really need to provide written assembly instructions and make following them part of the purchase terms. But my experience is that especially on larger orders a certain number of the parts will be dropped and thus not loaded by the pp tool. These then get hand loaded and can be put in rotated 180 degrees very easily. Another example of the fifty fifty rule. Given two choices I will pick the wrong one 80 percent of the time. Given one choice the odds of being correct only improve to about 70 percent. It got to the point that we require each board come with a tag telling us which parts were hand loaded so that we could visually inspect the board before power up. Steve Meier On Fri, 2008-07-18 at 23:00 +0100, Peter Clifton wrote: On Fri, 2008-07-18 at 11:45 -0700, Dave N6NZ wrote: Steven Michalske wrote: Worked almost right away. Note red wire and missing pullup. Keeps me humble. Green wires are less humbling, i suggest them. I look at design efforts like golf. Low scores are better, but nobody plays a round with 18 holes-in-one in a row. My most humbling: back in the 1980's I wrote an ECO with about 15 lifted pins and 50 or so red wires, a chip glued onto the board dead bug style, plus a piece of coax (!). (Didn't catch *that* case in simulation) This on a board with about 180 TTL packages. I just got a board back which the assembler rather keenly produced from draft files I'd sent during initial discussions. Clearly labelled next to one part with silk-screen on the board BUG: CAPACITOR SILK +/- SWAPPED (discovered during in-house prototyping, but I'd not got around to fixing it when I sent the draft files). They stuffed the capacitor according to the silk (wrong), and didn't notice / think to check with me what this strange silk-screen text was about! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Success with gEDA tools...
Hard responding after the next couple of irelevent repies... tears in my eyes from laughing... ok sure we expect the assembly shop to do their job perfect but they seem to come back with any excuse to justify why they are late. Uhm I am not sure we are much better with our custimers human nature and all. politics to boot. Steve M. Steve Meier wrote: Reversed polarized cap? Those ones are easy to find upon power up :) I don't think it is sufficient to rely upon the silk screen to provide assembly instructions. For cases like this you really need to provide written assembly instructions and make following them part of the purchase terms. But my experience is that especially on larger orders a certain number of the parts will be dropped and thus not loaded by the pp tool. These then get hand loaded and can be put in rotated 180 degrees very easily. Another example of the fifty fifty rule. Given two choices I will pick the wrong one 80 percent of the time. Given one choice the odds of being correct only improve to about 70 percent. It got to the point that we require each board come with a tag telling us which parts were hand loaded so that we could visually inspect the board before power up. Steve Meier On Fri, 2008-07-18 at 23:00 +0100, Peter Clifton wrote: On Fri, 2008-07-18 at 11:45 -0700, Dave N6NZ wrote: Steven Michalske wrote: Worked almost right away. Note red wire and missing pullup. Keeps me humble. Green wires are less humbling, i suggest them. I look at design efforts like golf. Low scores are better, but nobody plays a round with 18 holes-in-one in a row. My most humbling: back in the 1980's I wrote an ECO with about 15 lifted pins and 50 or so red wires, a chip glued onto the board dead bug style, plus a piece of coax (!). (Didn't catch *that* case in simulation) This on a board with about 180 TTL packages. I just got a board back which the assembler rather keenly produced from draft files I'd sent during initial discussions. Clearly labelled next to one part with silk-screen on the board BUG: CAPACITOR SILK +/- SWAPPED (discovered during in-house prototyping, but I'd not got around to fixing it when I sent the draft files). They stuffed the capacitor according to the silk (wrong), and didn't notice / think to check with me what this strange silk-screen text was about! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hierarchial refdes vs. board assembler
This might be one of the advantages for living in silicon valley. Competition probably drives the non-capable out. Bob Paddock wrote: On Wed, Jul 16, 2008 at 3:51 PM, Steve Meier [EMAIL PROTECTED] wrote: Also, if you layed out a section and then duplicated it to make exact copies their task should be easier not harder. I've been on the other end of this at a CM. Make sure your designators are unique through out a board or you will get hosed at some point in the process. Some PP and flying probe machines come with software that just down right suck. Doing something like X3/R2 could make it do something as stupid as try do divide the designators. X3-R2 might get you subtraction. X3R2 should be safe as a simple string. Program the pick and place for that section duplicate the program with the correct translation. The pay level for this might be around the level of Trained Monkeys. Anything that upsets the flow in the end is going to cost you more to get your board if they have to call in the Monkey Trainer. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hierarchial refdes vs. board assembler
This process as written below should be captured into the geda wiki. I do think the cost of the components is a hudge cost driver for a pcb assembly! However, the shop I primarily use for complex hierarchical boards with bga's of over 1000 pins has no problem with the hierarchical refdes. They can take the xy text file and program their Pp machines just fine. The flying probe tester is another issue. For the flying probe they need to know the location of each pad and each expossed via and request the pad's ascii file format. Side project has been to see if I can translate back and forth between pad's ascii and pcb... I have made considerable progress from pads to pcb. One suggestion I have is when approaching a shop tell them up fron you are using pcb an be ready to explain that it is an open source program. Check to see that they can handle the gerbers. This seems not to be an issue these days but still. Check to see that they can handle your refdes scheme. Better to have them agree up front then for them to use it as an issue to delay your boards. This might actually also be a good project for the wiki. A standard format rfq which defines our requirements. Steve Meier Bob Paddock wrote: They won't get my business again, as this crap is costing me a great deal of time - I wrote the message below for a different list last year, when someone wanted to know why getting a board built by a CM cost so much more than the parts cost when bought from DigiKey. It will give you lots to think about when picking a CM. If you can, pick one where you can go and see the place for yourself. I'm actually surprised your X3/R1 made it all the way to the PP machine before one of the CM's Systems barfed. Usually your BM is entered near the front of the process so your job can be quoted. === Is there a rule of thumb for estimating the cost of getting circuit boards assembled? In a past life I worked for a large Contract Manufacture, http://www.matrc.com . I don't mean this to a plug for them, but the tour of the place is helpful for the discusion: http://www.matric.com/tour.html http://www.matric.com/info/tour/smt.htm To a CM it is all about *Time*. When it comes to parts, the actually part cost is really insignificant as far as cost contribution goes. Most of the cost goes to the time it takes to setup and teardown. For a broad brush overview of cost steps: One shot fee for getting your project into the system. Someone has to enter your BOM, and schedule into the amourphys blob known as The System. Any change that you do triggers a recalculation, that you either payfor or is amortized across your boards. Every future order you place will have a small trigger few to pay for someone to enter your order. Included in that is a fee for someone to do a time analyze of the number of operations that your project will require. A unit time value is assigned to each operation, and each operation has a cost, that is, as far as I know, calculated by Magick (All CM's use Magick for this step to my knowledge). If you supply the parts there will be fees for entering a carrying fee per new part number into The System. Some cost analysis guru at GM, long ago, decided to simply have a number in The System carries a charge of $50 or so per year. The accountants just love to beat up the engineering department for we have to many parts in the warehouse. Company owner wants to keep inventory turnover high. Also cost for physically getting your parts into The System, such has putting them in the warehouse, typing in the data etc. There will be a scrapping fee to get your stuff out of The System if you take your project someplace else. Those None Recurring Engineering (NRE) fees you either pay for up front, or it is amortized across the number of boards. This is why the range can seem so different between different CMs. Some hide the fees, some don't. Also when you supply the parts the price of each part will be market up by a *minimum* of 33% (More Guru calculations). If you don't mark the price up by this amount you lose money each time you touch the part. You are changed for the use of the warehouse space, like renting a storage unit. Now lets say you let the CM supply the parts. In general this will get you a lower per part cost for the commodity parts. As they will be using 100,000 0.1 uF 0603 caps a day, the pick and place machine will have that loaded. So you don't have to pay for loading your reel of much smaller volume part. Also the CM will have negotiated a much better price than you got from Digikey. The downside here is that you lose some measure of control, which can be a problem if you have to meet UL/MSHA/FDA etc. regulations. Which reminds me there will be extera charges for projects that involve the pain of FDA paperwork, such a per lot tracking etc. Other
Re: gEDA-user: Hierarchial refdes vs. board assembler
I have found they need a little education and then seem fine with it. There is no shortage of assembly shops and so they tend to be willing to work with their customers. Steve Meier On Wed, 2008-07-16 at 17:53 +0100, Peter Clifton wrote: Hi guys, I'm having a board made at the moment which uses hierarchy in its refdes.. X3/U2, X2/R12 etc.. The assembly house who are building this didn't seem to appreciate the X2/ part of the refdes, apparently it is causing them problems programming their pick and place machine. They suggested renumbering things without the hierarchy. Apparently it will make life much easier and prevent mistakes. Has anyone else found assemblers with a dislike this kind of hierarchical refdes? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hierarchial refdes vs. board assembler
Also, if you layed out a section and then duplicated it to make exact copies their task should be easier not harder. Program the pick and place for that section duplicate the program with the correct translation. Steve Meier On Wed, 2008-07-16 at 17:53 +0100, Peter Clifton wrote: Hi guys, I'm having a board made at the moment which uses hierarchy in its refdes.. X3/U2, X2/R12 etc.. The assembly house who are building this didn't seem to appreciate the X2/ part of the refdes, apparently it is causing them problems programming their pick and place machine. They suggested renumbering things without the hierarchy. Apparently it will make life much easier and prevent mistakes. Has anyone else found assemblers with a dislike this kind of hierarchical refdes? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: size of 0402 footprint
Chip resistors: Length = Pad Length + pad separation + Pad Length in mm Package Length min 1.00 Length max 1.10 pad separation min 0.40 pad separation max 0.70 Width min 0.48 width max 0.60 pad length min 0.10 pad length max 0.30 height max 0.40 Chip Caps Length min 0.90 Length max 1.10 pad separation min 0.30 pad separation max 0.65 Width min 0.40 width max 0.60 pad length min 0.10 pad length max 0.30 height max 0.60 Inductors smallest inductor in the SM-782A spec is the 2012 On Mon, 2008-07-14 at 12:21 +, Kai-Martin Knaak wrote: On Mon, 14 Jul 2008 00:55:33 -0400, DJ Delorie wrote: What's the difference between the RES, CAP, and IND variants? http://lilalaser.de/tmp/1005_footprints_in_geda_lib.png The gap seems to be smallest for inductors and largest for resistors. Pad size is different too. ---(kaimartin)--- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: size of 0402 footprint
If you are hand assembling get some extra parts too. If you are building by pick and place the extar parts will be built into the length of tape you are required to provide the shop. DJ Delorie wrote: My next project will take into the realms of the barely visible: 0402's are huge compared to 01005's. http://www.delorie.com/pcb/smd-challenge/ http://www.delorie.com/pcb/smd-challenge/insanity_II.jpg The majority of parts will be populated by a third party in a reflow oven. I guess, they are ok with the small size footprint. They even told me not to choose large footprints as this would encourage tomb stoning. However, I will need to manually rework some of the more sensitive resistors. Would that be possible with the small size footprints? There are three standard 0402 sizes - least copper, normal, and most copper. Non-standard sizes may be significantly bigger to allow for manual soldering. Look for the INDC1005[LNM] footprints in ~geda. Choose the N size unless you have a good reason to do otherwise, especially with third-party automated paste/place/soldering. As for rework, get a hoof tip for your iron that's big enough to touch both ends of the top of the 0402 at the same time. The part should just stick to the iron and you can lift it off. Alternately, invest in something like the Metcal Talon, which has two tips to act like tweezers. Metcal also has a C shaped tip that can heat both pads at the same time. For the really small parts, heating one end is enough as conduction heats the other end. Hard on the part, but if you're going to toss it anyway... You'll want needle-end tweezers too. And a magnifying visor. In any case, having a bigger pad will not really help you rework these. They're too small for the pad to really help; you'll always be working from the top or sides of the part. Heating both ends at the same time is the key to reworking these small parts. Even with bigger pads, you can control tombstoning (somewhat) by controlling your paste mask. PCB doesn't have an editable paste mask, so you'll end up writing a script to go through one .pcb and twiddle the pads to make a second .pcb from which you'll export the paste mask. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Way OT: Architectural CAD programs (moving further left)
Yea that is what I was thinking. My wife is a geologist and while she makes heavy use of ESRI GIS programs for mapping complex geology, faults, land slides etc. When it is time to do the cross sections she uses Adobe Illustrator. CAD seems good at representing very exact ideas it seems not as capable at representing ambiguity when representing ambiguity is needed. However, I believe the professionals are moving away from paper but personally I am a clutz at illustrator like apps. Hmm and not much better with a white board. OK I mentioned a couple of proprietary programs so for the open source competition there is GRASS for GIS and there are at least a couple of illustrator like applications. GIS is geographical information system and is where your data has location information associated with it. So you shove your data into a database and then can plot the data out onto a map. There are also a number of other simulation and analysis packages you can run against the data. Steve M. DJ Delorie wrote: Yeah, he says the problem is that for certain types of engineering problems, the software just isn't flexible enough to properly deal them. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Hybrid hierarchy
I ran into a similar situation where i was splitting a complex fpga up across sub-sheets. I added a parameter hierarchy_disable = 1 to each symbol that I didn't want to expand the hierarchy. I of course am running a non-standard netlister. I have a recent version of my netlister that supports reasonably current gschem schematics and symbols. hierarchy_disable allows the netlister to continue processing sub symbols it just stops adding hierarchy tags to the fromt of each refdes another parameter no_bom says that a particular symbol should not be added to a bom as a unique component. So i pick one fpga sub-symbol for bom creation and all the rest for that device get the no_bom tag. If you run into problems with the standard netlister let me know and I will release a version of my nonstandard one. Best Wishes, Steve Meier On Fri, 2008-06-27 at 20:52 +0100, Peter Clifton wrote: Hi, I'm working with a moderately complex design which uses a about 3 levels of hierarchy in places. In others, I simply increment part-numbers between sheets. I've got a situation where I want to disable hierarchy mangling for a single instantiated module, a relay bank (X1) inside one of my output stages (X5). The relay bank is defined with a hierarchy block, 8x pages (autogenerated) which have relays tied to the appropriate IO symbols with refdes as appropriate to the symbol which represents this block. This gives X5/X1/K1 X5/X1/K2 etc... What I'd like to do is instantiate this block without any /X1 in the refdes. IE.. turn name mangling off for this specific entity. I tried deleting the refdes=.. attribute for that block, and gnetlist then treated the block's contents as top-level entities (K1, K2 etc..). I'm about to patch my gnetlist to keep the prefix up to this point, such that they become: X5/K1, X5/K2 etc.. Does anyone have any opinion as to whether this is sane? (Future controls on such an instantiated block might be nice such as having it respond to attributes such as refdes_add=100 (to alter block internal refdes in a different way). Regards, ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pin 1 placement in footprint
DJ is right you can put it where ever you want. However some assembly shops would like to know where the center of the foot print is. Steve Meier On Wed, 2008-06-25 at 18:02 +0200, Tamas Szabo wrote: Hi, I just checked the footprint in newlib and found that in lot of the cases pin 1 of a part is placed to (0,0). Is there any drawback if I put it somewhere else due to make the calculation easier? I mean, for example, selecting one corner of the outline of a module built on a small pcb (like GPS-, BT-modules) or connectors, etc., since all unit are measured from that point? Thx, /sza2 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hierarchy refdes's
room for ambiguity. sheet 2 as a subset of a higher level sheet 2 would become 22R21 sheet 22 could have a an R21 so another component becomes 22R21 Steve Meier On Fri, 2008-06-20 at 15:41 +, Kai-Martin Knaak wrote: On Tue, 17 Jun 2008 05:29:20 -0400, gene wrote: I just need to figure out how to handle the silkscreen. There's a thread on this subject somewhere that I ran across while googling last night. There is a couple of hierarchy related settings in system-gnetlistrc. You can set them to values other than the default in $HOME/.gEDA/gnetlistrc . Currently, mine looks like this: (hierarchy-traversal enabled) (hierarchy-uref-mangle enabled) (hierarchy-uref-separator ) (hierarchy-netname-mangle enabled) (hierarchy-netname-separator ) (hierarchy-netattrib-mangle disabled) (hierarchy-netattrib-separator /) (unnamed-netname noname) I set the uref seperator to an empty string. For minimum kludge of component names I set the uref of hierarchy symbols to pure, single digits. That way the uref of a component R21 from a sub sheet number 2 translates to 2R21. ---(kaimartin) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hierarchy refdes's
Wouldn't it be nice if the fab shop were to use a different color solder mask for each block On Tue, 2008-06-17 at 18:41 +0100, Peter Clifton wrote: On Tue, 2008-06-17 at 05:00 -0700, Steve Meier wrote: I don't know if pcb supports this but... In the Mentor Graphics Pads program you can make the refdes strings invisible and manualy replace them with strings. Each hierarchical block gets a silk screen line drawn around it. The block gets a string naming its hierarchy Thus you would have a block labled X12 and within that block a resistor labled R12 That was how I was thinking of doing my board. PCB does support showing the description or value instead of refdes. gsch2pcb uses description to stash the package it has used, so this is out. The netlister does correctly transfer value=... attributes, so it would be possible to hack around this by using value=R1 or something like. A further option would be to modify the netlister script to take from shortrefdes=... or even to intelligently strip off the suffix from the real refdes. The fact this ends up in PCB's value field does strike somewhat as a kludge though, and you wouldn't get any automatic zoning of hierarchy levels. I did think of modifying PCB's netlist view code to treat / as a hierarchy separator, and make a tree of nets to view. For large designs, that could be useful. Best wishes, ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Connecting AGND with GND
Take a look at your data sheet for the ADC often these devices will require both analog and digiital ground and often they will recomend you connect the two grounds close to them. Second I try to keep the digital ground away from the analog sections. Third try to avoid traces (requiring impedence matching) crossing over moats. I have been using surface mount power inductors to connect the two grounds. e.g coilcraft SLC7530 Steve Meier Stefan Salewski wrote: Hello, I have a net called AGND for sensitive analog signals, and one net GND for general purpose. Of course I have to connect these two nets (at one single, central point). Nets AGND and GND should be really different nets, because this will help me when I do the board layout (will ensure connection at one single, central point). So I have connected AGND and GND symbols with a resistor symbol in schematic, with zero OHMs and small SMD footprint. Is there a better way, i.e. substitution for this zero Ohm resistor? I think a footprint with two very small, overlapping pads may be an improvement? Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Connecting AGND with GND
Maybe. Noise levels generally apear to be different. The reducing of the connection between the two planes is probably as effective. One advantage of the inductor is that you can break the path entirerly if you have a problem. I tend to do this a lot with subsections of a complex board. Each section has its own filtered power supplies (inductor and caps). Again have a problem with the board start depowering sections of it by removing inductors. Or better yet power the board up one section at a time. I would like to re-iterate. Read the data sheets paying attention to the layout and groundiing sections. High Frequency circuits can break into oscillation very easily. There is almost always a predictable reason and those reasons are found in the layout and grounding sections of the data sheets. This would be a cool feature for a cad package. having these sections encapsolated into the symbols and land patterns. Then as you are laying them out to be able to get a report. Steve Meier Dave McGuire wrote: On Jun 17, 2008, at 6:49 PM, Steve Meier wrote: Take a look at your data sheet for the ADC often these devices will require both analog and digiital ground and often they will recomend you connect the two grounds close to them. Second I try to keep the digital ground away from the analog sections. Third try to avoid traces (requiring impedence matching) crossing over moats. I have been using surface mount power inductors to connect the two grounds. e.g coilcraft SLC7530 This is an interesting idea; do they serve as chokes to keep noise in one ground system from crossing over into the other? -Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Blind Buried Vias
having slept on this You can do this as a single project. But you need to split the plated cnc file up into two files. One file for your blind vias and a second for the vias that penetrate all layers. My understanding is that if you do this as a four layer board, the fab shop will build the first three layers then drill and plate them using the first cnc file. The fab shop will then add the forth layer and use the second cnc file to drill and plate the entire four layers. Check with your fab shop to verify. Steve M. Steve Meier wrote: Neil, Another way to do this is to break your design up into two boards or two sets of gerber files and then combined the two sets of gerbers into one complete set. The first set would have your top layer and all routing layers on it. The second set would contain your bottom layers. You will have to hand edit the cnc's move the vias that you require to punch through from the top to the bottom to the second set. Steve Meier Neil Webster wrote: Hi Steve, Sorry I should have described things better. The non-component side of the board has exposed pads that make deliberate contact with the body for a couple of selected nets on the PCB. All other nets on the PCB (eg power) can not be exposed on this side of the board. I had considered using tented vias to selectively isolate certain vias but I am concerned that this thin insulation layer could scrape off and expose the via. Regards, Neil On Sat, 2008-06-07 at 13:54 -0700, Steve Meier wrote: Neil, If the requirement is not to have the board not make electrical contact with skin, why not put an insulator on the back of the board? There are various types of tapes and even sprayes that can be used to encapsolate one or both sides. Steve Meier Neil Webster wrote: Hi all, I have an application where I am creating a small PCB as the basis of an active electrode. The non-component side of the board is in contact with skin and exposed vias on this side of the board therefore must be avoided. In the previous generation of the design, the circuit was simple enough to allow me to perform routing purely on the top surface. However the new design is significantly more complex and I think I will need to move to a multi-layer board. I therefore need blind vias. The official PCB documentation says that these are not supported. Extract from section 2.2: Each via exists on all copper layers. (i.e. blind and buried vias are not supported) However I did find a number of threads on this topic in the archive, one of which is referenced below. However this was almost 1 year ago and there may have been further developments. http://www.seul.org/pipermail/geda-dev/2006-July/000135.html Is there any way to achieve this with pcb? Regards, Neil ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Using mm units in .pcb files
I would like a base unit that supports both metric and English units and that allows me to pick a grid such that the pads of metric parts and English parts always center (with a reasonable tolerance) upon the grid Allowing me to snap traces to the grid for boards with both types. Steve Meier On Tue, 2008-06-10 at 15:00 -0700, Larry Doolittle wrote: Steven - On Tue, Jun 10, 2008 at 02:57:33PM -0700, Steven Michalske wrote: Remember the high school science teacher docking points for not using units? It's burned into my skull! What unit should we define for PCB default units? They are mill/100, one hundred thousandth of an inch, or a dmil; deci-mil ha ha a pun for a unit :-P Nice try, but 1/100 of a mil is a centi-mil. FIrst p0st! - Larry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
