Hi everyone, thanks you for your comments.
I have installed matlab 2013a, and tut3.slx was oppened, but when I compile
it (run xps) I get the following error
-
Failed to find 'XSG core config' in library 'xps_library' referenced
by 'tut3/XSG
core config'
-
So I'm working in it.
With
Further, is the board clocking OK? -- I believe the initialization script
should give feedback on whether of not the FPGA's PLL has successfully
locked to the ADC clock, and what the current measured board clock is.
Cheers
Jack
On Wed, 29 Mar 2017 at 14:28 Matt Dexter
Is the design and lab setup consistent with the limitations documented at
https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations
?
More information on the clock requirements may be found at
Yes ! I assume the clock has been clocked. For convenience, I have included
the output script i get after I run the initialization script.
Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
Gateware supports demux modes
I like the triumphant "done!" at the end :)
Next questions --
What version of the adc repo and mlib_devel repos are you using?
Do you have other hardware you can test on? (It's very unlikely to be a
hardware problem, IMO, but worth checking if you can).
What ADC clock rate are you using?
Cheers
Hello Casperites,
I have been working on the ROACH-2 casper for the past few months. Now i
have started to capture values from the ADC 16x250-8 block. But, when I am
trying to run the initialization script, it gives me an error saying that
"chip 'x' chan 'x' lane 'x' no good taps found ". I am
Hi Jason
I got my hands on a JTAG. I went through the CASPER debricking tutorial
page but I dont understand how to use the converter script? Do you perhaps
know how to use it?
Thanks for all of your help
Heystek
On Mon, Mar 27, 2017 at 11:54 AM, Heystek Grobler
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