Hi Xavier,
I don't think there is. There should be! I'll add it to the infinite todo
list.
Here's a preview, which maybe someone more knowledgable with augment /
correct --
You can always send packets from the FPGA without tap_start (which starts
the tgtap CPU process). Either you can configure
Hi Xavier,
I believe all the "snap" blocks have been deprecated, in favour of the
newer "snapshot" block, which has integration in the software control
libraries. If you are having this problem in a collaboration supplied model
(it sound like you're doing tut2?) it will be updated in due course
Hi Colin,
I don't think many people are supporting windows, though there was an email
from a few hours ago --
https://www.mail-archive.com/casper@lists.berkeley.edu/msg06862.html --
which had a link to a windows-friendly repo version. Perhaps this would be
useful to you.
Jack
On Wed, 28 Jun
In regards to the second question I asked in my previous email, I have
solved the issue of being able to read the software registers and snapshot
blocks. I needed to write the correct values to the software registers
after programming in order to properly initialize the design.
Thanks,
Mark
On
Hi,
Thank you very much Jack.
Is there a documentation regarding the oneGbE and tenGbE packages where
those interactions between the Ethernet blocks and the ROACH2 CPU are
explained?
Just curious, is there any way to send GbE packages without the tap_sart,
using the fabric configuration only? I am
Hi everyone,
I am having trouble compiling tutorial 1 from the casper site.
I have come across a few errors for which I found solutions to in the mail
archive but I cannot find a solution to my current error.
"Running Bitgen.."
"*"
cd implementation
Hi Jack,
After a little trial and error, this worked for me. I got errors when I left
the opb bus the same, and I also tried setting it to opb3, which was not
created by an excessive number of yellow blocks. It seems like there has to be
a partially full opb bus so it gets created early on in
Hello,
There still appears to be an issue with the firmware version loaded onto
the Virtex 7. As the image below shows, after a power cycle the SKARAB
boots from the "multi-boot" image. However, once the .fpg file is uploaded,
the Virtex 7 reverts back to using the toolflow image.
Additionally,
Hi Colin,
It looks to me like your design is compiling fine (generating the .bit and
.bin files), but that there is a issue with the final script that turns the
.bin file into the .bof file that we load onto the hardware.
Under the model directory, there will be an XPS_ROACH_BASE (or
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