you all never worried about cern before? why start now? better to just
keep focused on your current customers then unknown future additional
users.
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wouldn't it be nice to be able to tell a polygon that it belongs to a
net and the have the thermals that disagree highlighted?
On Fri, 2011-09-02 at 15:13 +1000, Stephen Ecob wrote:
Usually, when I have power and ground shorted, it's because of a via placed
some where that was accidentally
I am happy that doc is still useful.
Best Wishes to All here at geda,
Steve M.
On Wed, 2011-08-17 at 08:44 -0500, kqt4a...@comcast.net wrote:
On Tue, 16 Aug 2011, Colin D Bennett wrote:
On Tue, 16 Aug 2011 15:35:46 -0500 (CDT)
kqt4a...@comcast.net wrote:
I am sure this has been done
Must it be round?
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and place
equipment as well as their flying probe testers. Plus if you wan't to
translate projects back and forth between commercial cad programs this
seems to be the most commonly supported format.
Steve Meier
On Wed, 2009-05-13 at 16:01 -0500, John Griessen wrote:
al davis wrote:
My proposal does
Good: I like the arrows showing the problem.
Wrong location: The reason (i.e. Annular rings that are too small may
erode during etching) belongs in the area that you establish the design
rule check guidelines.
Steve Meier
On Sun, 2009-03-29 at 16:21 +0100, Peter Clifton wrote:
Hi guys
Notice that BRL CAD did make the cut. Why solid modeling but not EDA?
On Thu, 2009-03-19 at 11:41 -0500, John Griessen wrote:
Stuart Brorson wrote:
Hello --
I am unhappy to announce that the gEDA Project's application to the
Google Summer of Code was turned down this year.
This
has to be applied to a pin is dependent on
the size of the effective heat sink.
Seems to me that a single formula for calculating thermals is to
restrictive.
Steve Meier
On Mon, 2009-03-16 at 07:58 -0400, Ethan Swint wrote:
IIRC, it has to do with both the annulus width as well
Take a look at:
http://sourceforge.net/project/screenshots.php?group_id=201957
I think it would be cool to be able to select a couple of traces from
pcb and insert their info into an application like the above. perhaps
have some code that would follow the traces and every time one of the
traces,
This is a chicken and egg problem.
With revenue in the billions the major eda tool companies have far more
resources to keep developing capabilities.
On Fri, 2009-01-30 at 10:23 -0700, John Doty wrote:
On Jan 29, 2009, at 11:40 PM, Steve Meier wrote:
Let us be clear on this concept
When Jobs and Wozniak were tinkering in that garage, the dominant
computer hardware was System/370. They were wise not to try to
compete with that.
jobs and woz used a disruptive technology (the integrated circuit) to
compete with the bigger hardware.
And FOSS is disruptive
John,
Mentor Graphics provides schematic and board level translators
www.mentor.com/products/pcb/pads/translators
Altrium does as well and did about 55 million in sales last year.
https://wiki.altium.com/display/ADOH/Moving+to+Altium+Designer+From
+OrCAD
Steve Meier
On Fri, 2009-01-30 at 13
to programmer their flying probe
tester. (translating PCB to and from pads ascii is one of my side
pprojects)
Steve Meier
On Fri, 2009-01-30 at 16:55 -0700, John Doty wrote:
These are importers, but you were talking about exporters before. But
yes, there's more support for interoperabilty than I
Specifically, exporting netlists to just about any other tool
is a radical strength.
That's a *specific* problem, of narrow interest
Where as I WAS! (and will no longer) talking about the general issues of
having to share work with others like open office can with MS office.
Steve Meier
:32 -0700, John Doty wrote:
On Jan 30, 2009, at 6:16 PM, Steve Meier wrote:
Specifically, exporting netlists to just about any other tool
is a radical strength.
That's a *specific* problem, of narrow interest
Where as I WAS! (and will no longer) talking about the general
issues
GEDA is a Shark in a very small pond.
On Fri, 2009-01-30 at 18:32 -0700, John Doty wrote:
On Jan 30, 2009, at 6:16 PM, Steve Meier wrote:
Specifically, exporting netlists to just about any other tool
is a radical strength.
That's a *specific* problem, of narrow interest
Where
in one motion.
To hit shift h and then d to descend a hierarchical structure takes two
key strikes.
Steve Meier
On Tue, 2009-01-27 at 19:06 +, Peter Clifton wrote:
On Tue, 2009-01-27 at 18:55 +, r wrote:
*Personally*, I'm not a big fan of two-key shortcuts. They tend to
slow down
No Peter NO
DJ might just design a keyboard with keys as small as 1005s just to see
who could use it.
Steve M.
On Wed, 2009-01-28 at 00:08 +, Peter Clifton wrote:
On Tue, 2009-01-27 at 18:40 -0500, Dan McMahill wrote:
Peter Clifton wrote:
The 10 most common actions/operations were
can a 101 key keyboard fit on the paper strip of a paper match?
On Tue, 2009-01-27 at 18:25 -0800, Steve Meier wrote:
No Peter NO
DJ might just design a keyboard with keys as small as 1005s just to see
who could use it.
Steve M.
On Wed, 2009-01-28 at 00:08 +, Peter Clifton wrote
Orcad to KiCAD or Eagle. Then everybody in the free
software world will have to install geda.
Steve Meier
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is about the code, features, bugs and
documentation. Facebook and linkedin are about the people.
Steve Meier
On Sat, 2009-01-24 at 19:37 +, Peter Clifton wrote:
On Sat, 2009-01-24 at 18:51 +0100, Giuseppe Dia wrote:
Hi there,
thanks for your prompt answer. Didn't want to stir a debate
themselves the official whatever fan club or use the
copyrighted work of others without their permission.
Can you imagine if every linux user group had have Linus's blessing?
Poor Linus would be over whelmed.
Steve Meier
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geda
just this afternoon, I was contemplating this same issue
(starting a linkedin group) for a mountaineering club I have long been a
member of.
Steve Meier
On Fri, 2009-01-23 at 21:51 -0500, Ales Hvezda wrote:
[snip]
OK, but you can see where this idea creeps in: people wanting
to work
;) I did and responded before you did.
Steve M.
On Fri, 2009-01-23 at 22:39 -0500, Ales Hvezda wrote:
[snip]
so what is off topic?
Very little it seems. If you read my e-mail again, I didn't say anything
was off topic. I just don't want to see another debate on the license,
since it
This reminds me of two facts of saturation magnetic recording on
rotating (disc) media. You can only have an even number of transitions
around a track. Also, as much as test engineers would like to both
surfaces have to be spun at the same rpm.
On Thu, 2009-01-22 at 13:02 -0500, DJ Delorie
would clean up for a previous bad run.
Steve Meier
On Sat, 2009-01-17 at 07:37 +, Peter TB Brett wrote:
On Saturday 17 January 2009 02:43:44 Steve Meier wrote:
hmmm, isn't problem info being logged. I would agree if during the
current run the logfile only included warnings.
99
Amen
On Sat, 2009-01-17 at 10:56 -0500, Ales Hvezda wrote:
Currently, running any gEDA suite program leaves behind a log file in
the current working directory. I would like to change the default to not
generating log files, so that I (and other users who use the default
configuration) don't
hmmm, isn't problem info being logged. I would agree if during the
current run the logfile only included warnings.
how about if at the end of execution that if there was a problem of some
class detected that the user be asked if the log file should be
retained?
On Fri, 2009-01-16 at 18:32
and might have saved me the aforementioned accusation of
generating corrupted files if my compatriots had had and had known how
to read project build log files.
A modern fable by
Steve Meier
On Fri, 2009-01-16 at 19:53 -0700, John Doty wrote:
On Jan 16, 2009, at 7:43 PM, Steve Meier wrote:
hmmm
.
If the next application doesn't support the paste then of course I would
like that LOGGED.
Steve Meier
On Fri, 2009-01-16 at 21:25 -0700, John Doty wrote:
On Jan 16, 2009, at 8:48 PM, DJ Delorie wrote:
A program should do one thing well. Capturing circuit information
(regardless of what
Do either of you think that one size shoe should fit all peoples feet?
The market place of jobs will have opportunities for specialists and for
generalists and for ranges in between.
The generalist will be at a disadvantage when faced with a task that
pushes state of the art for a specific
John,
That was eloquently said.
I would suggest that geda/gaf users at a minimum should attempt to
understand the scripting language scheme and its interface to gaf.
Steve Meier
On Wed, 2009-01-14 at 20:30 -0700, John Doty wrote:
On Jan 14, 2009, at 6:43 PM, Joerg wrote:
But I can only
Well ~25 years ago, you didn't need no stinkin layout program you just
wire wrapped from the net list which was hand generated. I still have
holes in my fingers from those bloody pins.
On Tue, 2009-01-13 at 16:00 -0500, DJ Delorie wrote:
Sure, but I don't think that's what gEDA was meant to
productive. One
management technique that I have learned (I think in the army) is that
some talks with people should be done one on one and not as a dressing
down in public!
Steve Meier
On Mon, 2009-01-12 at 17:43 -0500, Ales Hvezda wrote:
All,
Oh no, not again... We have already had
I would caution.
That labeling of a company as evil just because they are offering use of
proprietary tools, will probably turn off a lot of companies that you
would like to sponsor geda.
Show the corporate world that geda is more flexible, a strong supportive
user base, support for simulation
The stock libgeda supports net type or bus type pins. I would just make
it an option when editing a pin. Make the default type a net type.
Current gschem behavior of a bus type not being able to connect to a net
is fine
thanks,
Steve Meier
On Fri, 2009-01-02 at 20:48 +, Peter Clifton wrote
into a single potentially massive
undrawable page.
Then the output script is run
This currently supports PCB and PADS netlists
-g PCB
-g pads
If you try this out before the end of the first week of january... well
you have my best wishes.
Steve Meier
On Fri, 2008-12-26 at 03:27 -0800, Yamazaki R2
)
do you need to support non-usb flash memory (like from your digital
camera)
other then that get it loaded with dram and disk space.
have fun,
Steve Meier
On Fri, 2008-12-26 at 04:54 -0800, Larry Doolittle wrote:
Stuart -
On Fri, Dec 26, 2008 at 07:33:13AM -0500, Stuart Brorson wrote
appreciate it.
Thanks,
Steve Meier
On Fri, 2008-12-19 at 18:09 +, Peter Clifton wrote:
On Fri, 2008-12-19 at 18:13 +0100, Oliver Florian wrote:
Hi,
@Ales:
Thanks for the statement, alone the certainty helped me a lot, really.
@Steve:
Thank you very much for your interest (sorry
Me thinks the odds of an ice storm in both Texas and New Hampshire
concurrently is very low
On Thu, 2008-12-18 at 12:43 -0500, DJ Delorie wrote:
Thanks to John Griessen, gedasymbols.org now has a second server.
Normally, both servers are used, but in the case of yet another outage
at my house,
Steve,
Sure sounds like a good starting point.
Steve M.
On Wed, 2008-12-17 at 00:23 -0500, Steve Morss wrote:
A year or two ago, I made a footprint replacement program which worked
very well for me (I used it to swap out a few hundred parts with about
50 different footprints). It worked
another good starting point. and the added fun of competing
implementations.
On Tue, 2008-12-16 at 23:20 -0800, Dean Ferreyra wrote:
gene wrote:
That is, modify a footprint in a library then have it get updated on all
instances on the board - or at least be able to update a single
Yes. The weight of the ice on top of the wire was sufficient to twist
the wire upside-down.
No wonder I had to flip the symbols I just down loaded
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.
Seriously, this would be a good beginner project.
Steve Meier
On Tue, 2008-12-16 at 21:38 -0500, gene wrote:
That is, modify a footprint in a library then have it get updated on all
instances on the board - or at least be able to update a single
instance. Is this possible? I found some older list
For the advanced student do it as a plugin to pcb.
On Tue, 2008-12-16 at 21:40 -0500, DJ Delorie wrote:
That is, modify a footprint in a library then have it get updated on all
instances on the board - or at least be able to update a single
instance. Is this possible? I found some older
I was thinking that the pcb file format does have a specific place
components are found (in the pcb file). So a string comparison of the
old string against the searched for string should work.
Given that we found a match.
Can we align the old land pattern in terms of x-y translation and
Just to put it on the screen an example land pattern.
Element(0x00 Surface Mount Chip Resistor 0603 R0 0 0
-31 -82 2 100 0x00)
(
Pad(-2 0 2 0 39 30 50 pad 1 1 0x0100)
Pad(65 0 69 0 39 30 50 pad 2 2 0x0100)
ElementLine(-21 -35 87 -35 5)
ElementLine( 87
A good survey question:
What are the most common reasons that you need to change land patterns?
Steve Meier
On Tue, 2008-12-16 at 22:38 -0500, DJ Delorie wrote:
I could go a step further or two. Same number of pins? same number
of pads. same pin and pad pin numbers?
Each thing that must
The pattern I picked had the wrong dimensions.
The pattern I picked had the pin numbers wrong.
On Tue, 2008-12-16 at 19:42 -0800, Steve Meier wrote:
A good survey question:
What are the most common reasons that you need to change land patterns?
Steve Meier
On Tue, 2008-12-16
maybe we ought to set up a mirror.
Steve Meier
On Mon, 2008-12-15 at 19:59 -0500, John Luciani wrote:
The Northeast (U.S.) was hit with a major ice storm. IIRC
gedasymbols.org is on DJs server which is located in
NH. On the news tonight they were saying that some
NH customers may not have
Very cool. Is there a list of enhancements to be done as pert of this
project?
Steve Meier
On Sun, 2008-12-14 at 17:23 -0500, Stuart Brorson wrote:
Good news for gEDA users!
Please read the below press release, of interest to all gEDA users.
It has gone out to a variety of EE news sources
with each others
traces?
I am familiar with bga devices with pitches of 1mm and I have squeezed 4
mill pitch traces between rows to escape the device. More typically I
use a 4 mill width (now that pcb supports more then 8 layers)
Steve Meier
On Sun, 2008-12-14 at 21:30 -0500, gene wrote:
Steve
yep. Make the pcb work area larger then the board. add a silk screen
around the edge of the board or make a separate board layer and put the
outline there. Add a fabrication instruction to make the board to the
outline.
Steve M.
On Fri, 2008-12-12 at 20:08 -0800, David Griffith wrote:
Is
or send me
an example design? Along with comments about what your desired behavior
is?
Steve Meier
On Sun, 2008-12-07 at 02:26 +0100, Oliver Florian wrote:
Hi everybody,
I'm currently working on a netlister backend and I am desperately
looking for a solution regarding a problem with hierarchical
No no Peter that would let you off far to easy.
Your punishment for this infraction is the next 100 pieces of spam that
hit your in-box. Would should have occurred by right . now.
On Tue, 2008-12-02 at 12:27 +, Peter Clifton wrote:
On Mon, 2008-12-01 at 21:25 -0500, Dave McGuire
I tried, but the brake lever is stuck!
On Mon, 2008-12-01 at 21:30 -0500, DJ Delorie wrote:
Self-sufficiency has quite obviously gone out of style. Stop the
world, I want to get off.
See, now, if you were thinking clearly you'd want to stop the world so
everyone *else* could get off.
I am also sure, that somewhere within the windows vista operating system
is a universal reset. Where is that button?. There might be a similar
system call within linux but DJ is to worried about his clock to tell me
the key to the obfuscated code.
On Mon, 2008-12-01 at 18:41 -0800, Steve Meier
in
reference designators and in net names.
It would be a non-simple task to reconvert the hierarchical information
in the reference designators and nets back into a hierarchical format.
Steve Meier
On Wed, 2008-11-19 at 10:32 +, Peter Clifton wrote:
On Wed, 2008-11-19 at 10:23 +, r wrote:
Hi
Yamazaki,
I have done a fair amount of work on hierarchical netlisting. However, I
run my own customized versions of libgeda and gnetlist. In my version,
each page is netlisted separately and thus a back end could be written
to retain the hierarchical information.
Steve Meier
On Tue, 2008-11
The Pads ASCII format uses a base unit of 0.0002624671916 inches
which is 1.054 nM
Converting it to metric causes an error of about 0.5 nM
The PCB base unit is 0.1 inches
Converting it to metric causes an error of 19.7 nM
All I can figure out about why pads uses that weird number
).
Steve Meier
On Wed, 2008-11-19 at 10:22 -0800, Steve Meier wrote:
The Pads ASCII format uses a base unit of 0.0002624671916 inches
which is 1.054 nM
Converting it to metric causes an error of about 0.5 nM
The PCB base unit is 0.1 inches
Converting it to metric causes
1 in = 25.3972 mm not exactly 25.4 but close enough for layout
work if you use high enough precision.
25.4 to 1 might not be close enough if you are trying to put a satellite
in orbit around mars.
Steve M.
On Wed, 2008-11-19 at 18:58 -0700, John Doty wrote:
On Nov 19, 2008, at 4:08
/3937 meter or 1 yard = 0.914 401 8288 meter
Which works out to be 1 in = 0.025400051 m
Steve Meier
http://www.wsdot.wa.gov/Reference/metrics/foottometer.htm
On Wed, 2008-11-19 at 19:45 -0700, John Doty wrote:
On Nov 19, 2008, at 7:21 PM, Steve Meier wrote:
1 in = 25.3972 mm
I am pretty sure the answer is yes
Steve Meier
On Thu, 2008-11-13 at 13:45 -0500, Ethan Swint wrote:
Duncan Drennan wrote:
How about making use of the IPC-7351 footprint definitions instead?
You can grab the free PCB Matrix land pattern viewer and calculator
here, http
Can you attach an example KiCAD netlist?
Steve Meier
On Thu, 2008-11-13 at 22:01 -0200, Raphael Derosso Pereira wrote:
Is it possible at least? Then I could finish schematics in KiCAD and
begin layout on PCB.
--
Raphael Derosso Pereira
Engenheiro de Computação
icq: 4517421
I can't speak about all regions of the country let alone the world.
but yes ask ask ask why do you do that if you use that tool
what are the requirements
I did ask today, uhm looking at DJ's clock ok yesterday. The assembly
shop had a tool that would look around under the bga...
of the reflow oven? or wash or final inspection?
Steve Meier
On Fri, 2008-10-31 at 20:31 -0400, Bob Paddock wrote:
On Friday 31 October 2008 03:43:20 pm Joerg wrote:
Much better. If you want to be extra good provide another 0.1uF parallel
to the AVDD caps, close to pin 3. C13 in your
at 20:58 -0400, Bob Paddock wrote:
On Friday 31 October 2008 08:40:44 pm Steve Meier wrote:
If having to switch between nozzles is a significant issue then there is
room for a new pick and place equipment company that builds a
multi-nozzle tool.
They do exist of course, but there maybe
It isn't your clock that is pulling all that power is it?
Steve M.
On Fri, 2008-10-31 at 22:45 -0400, DJ Delorie wrote:
At the end of the day the only thing that counts is whether it's
good enough and it looks like DJ's board should perform pretty well
now.
And yet I keep improving it
Dave,
No I struggled three times to get usable url's so go down a couple more
of my attempts and then you will have to take the line breaks out of the
ultra long url but you can get there.
Steve Meier
On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote:
I don't see any URLs
Ok ok ok go to my home page and look for links to hs table of contents
and hs section 1 through 4
http://www.alchemyresearch.com/
Steve Meier
On Thu, 2008-10-30 at 16:29 -0400, Dave McGuire wrote:
I don't see any URLs in there..
-Dave
On Oct 29, 2008, at 6:08 PM, Steve Meier
. And the urls are convoluted.
Steve Meier
On Thu, 2008-10-30 at 19:14 -0700, Steven Michalske wrote:
Were you trying to format them with HTML?
I bet the HTML filters on the mailing list were cutting out the links.
On Oct 30, 2008, at 2:44 PM, Eric Winsor wrote:
Steve,
I don't see these other
On Tue, 2008-10-28 at 20:47 -0400, DJ Delorie wrote:
Joerg [EMAIL PROTECTED] writes:
By now I'd say Prehistoric Digital Assistant. The only guy I know
who actually still uses one is our pastor.
I have one I use every day, but it's in my watch.
So that watch isn't on a wrist band it is
I went looking to see if the Analog Device book was available
electronically. Here are the links.
Steve Meier
High Speed System Applications Table of Contents
High Speed System Applications Section 1: High Speed Data Conversion
Overview
High Speed System Applications Section 2
symbols are or how big your printer is it ain't readable.
Steve Meier
On Wed, 2008-10-29 at 18:22 -0400, Dave McGuire wrote:
On Oct 29, 2008, at 5:33 PM, John Doty wrote:
Should I adjust the size of the symbols or the size of title-B.sym?
What is the correct way and how do I do that?
I
.
There is a lot more talked about then just that one blurb.
Steve Meier
On Tue, 2008-10-28 at 11:22 -0700, Joerg wrote:
Stefan Salewski wrote:
Sometimes it is necessary/recommended to partition (separate) power or
ground planes, i.e. for ADC or DC/DC-Converters, see page 16 and 17 in
http
yes it helps immensely to have a low pass filter issolating a device
from the power planes.
Steve Meier
On Tue, 2008-10-28 at 14:49 -0400, DJ Delorie wrote:
In my 20+ years in engineering I have yet to see one case where
splitting a ground plane under high-speed ADCs has worked.
What
increase it over 1000 times. Any noise that crosses over from the
digital into the analog gets multiplied up by that gain as well.
Steve Meier
On Tue, 2008-10-28 at 15:02 -0400, Stuart Brorson wrote:
Sometimes it is necessary/recommended to partition (separate) power or
ground planes, i.e. for ADC
For non-hierarchical schematics all nets that have the same net name
attributes will be connected.
Steve Meier
On Tue, 2008-10-28 at 18:13 -0400, Rob Butts wrote:
I have a multi-page schematic. I named the schematic according to the
gschem guidelines name_pg#.sch. If I want to have a net
the power inductor or not. You can leave it open or you can
short it.
I also do similar activities for power supplies separating the board
power from board sections. Makes it very easy to debug the board from
one section to the next.
Steve Meier
On Mon, 2008-10-27 at 19:47 +0200, Duncan Drennan
of the board.
Steve Meier
On Mon, 2008-10-27 at 14:43 -0700, Steve Meier wrote:
I agree with Niel, I separate my ground planes with a symbol for a power
inductor. I do this at the schematic level and then I read the layout
suggestions typically provided by the A/D data sheet on where to connect
the gnetlist option -g tells genlist what backend file to use.
-g spice uses the file gnet-spice.scm
on my machine it is found in /usr/local/share/gEDA/scheme
it is also found in the gnetlist source code in the scheme directory
Steve Meier
On Thu, 2008-10-23 at 11:17 -0700, Yamazaki R2
to capture all of
this. My spread sheet is available upon request.
Steve Meier
On Thu, 2008-07-31 at 18:29 +0200, Philipp Klaus Krause wrote:
It seems the only way to deal with them is to create each footprint from
scratch eachtime I have to use one. Nearly eachtime I try to use an
existing
percent of the time. Given one choice the odds of being
correct only improve to about 70 percent.
It got to the point that we require each board come with a tag telling
us which parts were hand loaded so that we could visually inspect the
board before power up.
Steve Meier
On Fri, 2008-07-18
and all. politics to boot.
Steve M.
Steve Meier wrote:
Reversed polarized cap? Those ones are easy to find upon power up :)
I don't think it is sufficient to rely upon the silk screen to provide
assembly instructions.
For cases like this you really need to provide written assembly
This might be one of the advantages for living in silicon valley.
Competition probably drives the non-capable out.
Bob Paddock wrote:
On Wed, Jul 16, 2008 at 3:51 PM, Steve Meier [EMAIL PROTECTED] wrote:
Also, if you layed out a section and then duplicated it to make exact
copies
not to be an
issue these days but still. Check to see that they can handle your
refdes scheme. Better to have them agree up front then for them to use
it as an issue to delay your boards.
This might actually also be a good project for the wiki. A standard
format rfq which defines our requirements.
Steve Meier
I have found they need a little education and then seem fine with it.
There is no shortage of assembly shops and so they tend to be willing to
work with their customers.
Steve Meier
On Wed, 2008-07-16 at 17:53 +0100, Peter Clifton wrote:
Hi guys,
I'm having a board made at the moment which
Also, if you layed out a section and then duplicated it to make exact
copies their task should be easier not harder.
Program the pick and place for that section duplicate the program with
the correct translation.
Steve Meier
On Wed, 2008-07-16 at 17:53 +0100, Peter Clifton wrote:
Hi guys
Chip resistors:
Length = Pad Length + pad separation + Pad Length
in mm
Package
Length min 1.00
Length max 1.10
pad separation min 0.40
pad separation max 0.70
Width min 0.48
width max 0.60
pad length min 0.10
pad length max 0.30
height max 0.40
Chip Caps
Length min 0.90
Length max
If you are hand assembling get some extra parts too. If you are building
by pick and place the extar parts will be built into the length of tape
you are required to provide the shop.
DJ Delorie wrote:
My next project will take into the realms of the barely visible:
0402's are huge
Yea that is what I was thinking. My wife is a geologist and while she
makes heavy use of ESRI GIS programs for mapping complex geology,
faults, land slides etc. When it is time to do the cross sections she
uses Adobe Illustrator. CAD seems good at representing very exact ideas
it seems not as
pick one fpga sub-symbol for bom creation and all
the rest for that device get the no_bom tag.
If you run into problems with the standard netlister let me know and I
will release a version of my nonstandard one.
Best Wishes,
Steve Meier
On Fri, 2008-06-27 at 20:52 +0100, Peter Clifton wrote
DJ is right you can put it where ever you want.
However some assembly shops would like to know where the center of the
foot print is.
Steve Meier
On Wed, 2008-06-25 at 18:02 +0200, Tamas Szabo wrote:
Hi,
I just checked the footprint in newlib and found that in lot of the
cases pin 1
room for ambiguity.
sheet 2 as a subset of a higher level sheet 2 would become 22R21
sheet 22 could have a an R21 so another component becomes 22R21
Steve Meier
On Fri, 2008-06-20 at 15:41 +, Kai-Martin Knaak wrote:
On Tue, 17 Jun 2008 05:29:20 -0400, gene wrote:
I just need
Wouldn't it be nice if the fab shop were to use a different color solder
mask for each block
On Tue, 2008-06-17 at 18:41 +0100, Peter Clifton wrote:
On Tue, 2008-06-17 at 05:00 -0700, Steve Meier wrote:
I don't know if pcb supports this but...
In the Mentor Graphics Pads program you can
matching) crossing over moats.
I have been using surface mount power inductors to connect the two
grounds. e.g coilcraft SLC7530
Steve Meier
Stefan Salewski wrote:
Hello,
I have a net called AGND for sensitive analog signals, and one net GND
for general purpose.
Of course I have
into the symbols and land patterns. Then as you are laying
them out to be able to get a report.
Steve Meier
Dave McGuire wrote:
On Jun 17, 2008, at 6:49 PM, Steve Meier wrote:
Take a look at your data sheet for the ADC often these devices will
require both analog and digiital ground and often
the first three layers then drill and plate them using
the first cnc file. The fab shop will then add the forth layer and use
the second cnc file to drill and plate the entire four layers. Check
with your fab shop to verify.
Steve M.
Steve Meier wrote:
Neil,
Another way to do this is to break
I would like a base unit that supports both metric and English units and
that allows me to pick a grid such that the pads of metric parts and
English parts always center (with a reasonable tolerance) upon the grid
Allowing me to snap traces to the grid for boards with both types.
Steve Meier
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