> -Original Message-
> From: Marc Zyngier
> Sent: 18 May 2020 13:45
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Anup Patel
> Sent: 16 May 2020 21:59
> To: Marc Zyngier
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> F
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 18:46
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 19:01
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 17:59
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 18:01
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 17:50
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
> -Original Message-
> From: Marc Zyngier
> Sent: 16 May 2020 17:42
> To: Anup Patel
> Cc: Palmer Dabbelt ; Paul Walmsley
> ; Thomas Gleixner ; Jason
> Cooper ; Atish Patra ; Alistair
> Francis ; Anup Patel ; linux-
> ri...@lists.infradead.org; linux-kerne
We improve PLIC banner to help distinguish multiple PLIC instances
in boot time prints.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive
://github.com/avpatel/qemu.git
Anup Patel (4):
irqchip/sifive-plic: Setup cpuhp once after current handler is present
irqchip/sifive-plic: Improve boot prints for multiple PLIC instances
irqchip/sifive-plic: Separate irq_chip for muiltiple PLIC instances
irqchip/sifive-plic: Set default irq
.
This patch fixes both above issues.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index 822e074c0600..7dc23edb3267 100644
To distinguish interrupts from multiple PLIC instances, we use a
per-PLIC irq_chip instance with a different name.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/irqchip
tiple PLIC instances. To fix this, we now set "lmask" as the
default irq affinity in for each interrupt in plic_irqdomain_map().
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/dri
On Wed, May 6, 2020 at 9:26 AM Sagar Kadam wrote:
>
> Hi Palmer,
>
> > -Original Message-
> > From: Palmer Dabbelt
> > Sent: Wednesday, May 6, 2020 4:54 AM
> > To: Sagar Kadam
> > Cc: tudor.amba...@microchip.com; miquel.ray...@bootlin.com;
> > rich...@nod.at; vigne...@ti.com; Paul
CPUS] __section(.data);
> +void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
>
> extern const struct cpu_operations cpu_ops_sbi;
> extern const struct cpu_operations cpu_ops_spinwait;
> --
> 2.26.1
>
Apart from above, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Sat, May 2, 2020 at 11:30 AM Zong Li wrote:
>
> On Fri, May 1, 2020 at 2:23 AM Atish Patra wrote:
> >
> > On Thu, Apr 30, 2020 at 2:53 AM Zong Li wrote:
> > >
> > > Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> > > Currently, these two variables are put in bss
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
CC: Jonathan Corbet
CC: linux-...@vger.kernel.org
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.rst | 193 +++--
1 file changed, 184 insertions(+), 9 deletions(-)
diff --git
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Acked
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 81
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
which are forwarded to user space because these calls cannot be
implemented in kernel space. In future, when we implement SBI v0.2 for
Guest, we will forward SBI v0.2 experimental and vendor extension calls
to user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 25 +++
arch/riscv/kvm/Makefile | 3
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index 35101ba8814d..2384b4bf4939
of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/uapi/asm/kvm.h | 52 ++-
arch/riscv/kvm/vcpu.c
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 85
1 file changed, 85
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
atomic bitops instead
- Added separate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (13):
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy funct
On Wed, Oct 23, 2019 at 11:30 AM Paul Walmsley wrote:
>
> On Wed, 23 Oct 2019, Anup Patel wrote:
>
> > On Wed, Oct 23, 2019 at 6:37 AM Paul Walmsley
> > wrote:
> >
> > > Incidentally, just looking at drivers/platform/goldfish, that driver seems
> >
On Wed, Oct 23, 2019 at 6:37 AM Paul Walmsley wrote:
>
> On Tue, 22 Oct 2019, Alistair Francis wrote:
>
> > I think it makese sense for this to go into Linux first.
> >
> > The QEMU patches are going to be accepted, just some nit picking to do
> > first :)
> >
> > After that we have to wait for a
On Mon, Oct 21, 2019 at 11:01 PM Paolo Bonzini wrote:
>
> On 16/10/19 18:11, Anup Patel wrote:
> > Instead of dealing with PGD, PMD, and PTE differently in stage2
> > page table progamming, we can simply use iterative and recursive
> > helper functions to program stage2
On Mon, Oct 21, 2019 at 10:58 PM Paolo Bonzini wrote:
>
> On 16/10/19 18:12, Anup Patel wrote:
> > Currently, we track last value wrote to VSIP CSR using per-CPU
> > vsip_shadow variable but this easily goes out-of-sync because
> > Guest can update VSIP.SSIP bit direc
On Mon, Oct 21, 2019 at 10:57 PM Paolo Bonzini wrote:
>
> On 16/10/19 18:12, Anup Patel wrote:
> > + /* Read current VSIP and VSIE CSRs */
> > + vsip = csr_read(CSR_VSIP);
> > + csr->vsie = csr_read(CSR_VSIE);
> > +
> > + /* Sync
Hi Paul/Palmer,
On Thu, Oct 17, 2019 at 11:07 PM Christoph Hellwig wrote:
>
> Hi all,
>
> below is a series to support nommu mode on RISC-V. For now this series
> just works under qemu with the qemu-virt platform, but Damien has also
> been able to get kernel based on this tree with additional
gt; + riscv_cpuid_to_hartid_mask(, _mask);
> + sbi_remote_fence_i(cpumask_bits(_mask));
> + } else {
> + on_each_cpu_mask(, ipi_remote_fence_i, NULL, 1);
> }
>
> preempt_enable();
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
elta);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + sbi_set_timer(get_cycles64() + delta);
> + else
> + mmio_set_timer(get_cycles64() + delta);
> return 0;
> }
>
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
zero
> + fmv.s.x f29, zero
> + fmv.s.x f30, zero
> + fmv.s.x f31, zero
> + csrwfcsr, 0
> + /* note that the caller must clear SR_FS */
> +#endif /* CONFIG_FPU */
> +.Lreset_regs_done:
> + ret
> +END(reset_regs)
> +#endif /* CONFIG_RISCV_M_MODE */
> +
> __PAGE_ALIGNED_BSS
> /* Empty zero page */
> .balign PAGE_SIZE
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
/arch/riscv/mm/Makefile
> +++ b/arch/riscv/mm/Makefile
> @@ -6,9 +6,8 @@ CFLAGS_REMOVE_init.o = -pg
> endif
>
> obj-y += init.o
> -obj-y += fault.o
> obj-y += extable.o
> -obj-y += ioremap.o
> +obj-$(CONFIG_MMU) += fault.o ioremap.o
> obj-y += cacheflush.o
> obj-y += context.o
> obj-y += sifive_l2_cache.o
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 794c9ab256eb..8f1900686640 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -78,6 +78,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local)
>
> #endif /* CONFIG_SMP */
>
> +#ifdef CONFIG_MMU
> void flush_icache_pte(pte_t pte)
> {
> struct page *page = pte_page(pte);
> @@ -85,3 +86,4 @@ void flush_icache_pte(pte_t pte)
> if (!test_and_set_bit(PG_dcache_clean, >flags))
> flush_icache_all();
> }
> +#endif /* CONFIG_MMU */
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index beeb5d7f92ea..073ff12a838a 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -57,8 +57,10 @@ void switch_mm(struct mm_struct *prev, struct mm_struct
> *next,
> cpumask_clear_cpu(cpu, mm_cpumask(prev));
> cpumask_set_cpu(cpu, mm_cpumask(next));
>
> +#ifdef CONFIG_MMU
> csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE);
> local_flush_tlb_all();
> +#endif
>
> flush_icache_deferred(next);
> }
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 83f7d12042fb..0b063f6acaa1 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -24,6 +24,7 @@ unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned
> long)]
> EXPORT_SYMBOL(empty_zero_page);
>
> extern char _start[];
> +void *dtb_early_va;
>
> static void __init zone_sizes_init(void)
> {
> @@ -140,12 +141,12 @@ void __init setup_bootmem(void)
> }
> }
>
> +#ifdef CONFIG_MMU
> unsigned long va_pa_offset;
> EXPORT_SYMBOL(va_pa_offset);
> unsigned long pfn_base;
> EXPORT_SYMBOL(pfn_base);
>
> -void *dtb_early_va;
> pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
> pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
> pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
> @@ -448,6 +449,16 @@ static void __init setup_vm_final(void)
> csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | SATP_MODE);
> local_flush_tlb_all();
> }
> +#else
> +asmlinkage void __init setup_vm(uintptr_t dtb_pa)
> +{
> + dtb_early_va = (void *)dtb_pa;
> +}
> +
> +static inline void setup_vm_final(void)
> +{
> +}
> +#endif /* CONFIG_MMU */
>
> void __init paging_init(void)
> {
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
g_fault(SIGTRAP, TRAP_BRKPT, (void __user
> *)regs->sepc);
> + else if (report_bug(regs->sepc, regs) == BUG_TRAP_TYPE_WARN)
> + regs->sepc += get_break_insn_length(regs->sepc);
> + else
> + die(regs, "Kernel BUG");
> }
>
>
a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -24,6 +24,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -134,6 +135,9 @@ asmlinkage void __init smp_callin(void)
> {
> struct mm_struct *mm = _mm;
>
> + if (!IS_ENABLED(CONFIG_RISCV_SBI))
> + clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
> +
> /* All kernel threads share the same mm context. */
> mmgrab(mm);
> current->active_mm = mm;
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
_M_TIMER
> +# define INTERRUPT_CAUSE_EXTERNAL IRQ_M_EXT
> +#else
> +# define INTERRUPT_CAUSE_SOFTWARE IRQ_S_SOFT
> +# define INTERRUPT_CAUSE_TIMER IRQ_S_TIMER
> +# define INTERRUPT_CAUSE_EXTERNAL IRQ_S_EXT
> +#endif /* CONFIG_RISCV_M_MODE */
>
> int arch
csrr a0, CSR_MHARTID
> +#endif
> +
> /* Load the global pointer */
> .option push
> .option norelax
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
YCON_RISCV_SBI
> bool "Early console using RISC-V SBI"
> - depends on RISCV
> + depends on RISCV_SBI
> select SERIAL_CORE
> select SERIAL_CORE_CONSOLE
> select SERIAL_EARLYCON
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
f;
> + return 0;
> +}
> +early_initcall(sbi_init);
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
unsigned long addr);
> -
> -#endif /* !__ASSEMBLY__ */
> +void die(struct pt_regs *regs, const char *str);
> +void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr);
>
> #endif /* _ASM_RISCV_BUG_H */
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
size, asid);
> }
> -
> -#endif
> +#endif /* CONFIG_RISCV_SBI */
> +#endif /* _ASM_RISCV_SBI_H */
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
--git a/arch/riscv/mm/extable.c b/arch/riscv/mm/extable.c
> index 7aed9178d365..e0659deeb16b 100644
> --- a/arch/riscv/mm/extable.c
> +++ b/arch/riscv/mm/extable.c
> @@ -15,9 +15,9 @@ int fixup_exception(struct pt_regs *regs)
> {
> const struct exception_table_entry *fixup;
>
> - fixup = search_exception_tables(regs->sepc);
> + fixup = search_exception_tables(regs->xepc);
> if (fixup) {
> - regs->sepc = fixup->fixup;
> + regs->xepc = fixup->fixup;
> return 1;
> }
> return 0;
> diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
> index 96add1427a75..10a8ce38ac7a 100644
> --- a/arch/riscv/mm/fault.c
> +++ b/arch/riscv/mm/fault.c
> @@ -32,8 +32,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
> int code = SEGV_MAPERR;
> vm_fault_t fault;
>
> - cause = regs->scause;
> - addr = regs->sbadaddr;
> + cause = regs->xcause;
> + addr = regs->xbadaddr;
>
> tsk = current;
> mm = tsk->mm;
> @@ -51,7 +51,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
> goto vmalloc_fault;
>
> /* Enable interrupts if they were enabled in the parent context. */
> - if (likely(regs->sstatus & SR_SPIE))
> + if (likely(regs->xstatus & SR_XPIE))
> local_irq_enable();
>
> /*
> diff --git a/drivers/clocksource/timer-riscv.c
> b/drivers/clocksource/timer-riscv.c
> index 470c7ef02ea4..5d2fdc3e28a9 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -19,7 +19,7 @@
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> - csr_set(sie, SIE_STIE);
> + csr_set(CSR_XIE, XIE_XTIE);
> sbi_set_timer(get_cycles64() + delta);
> return 0;
> }
> @@ -61,13 +61,13 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
> ce->cpumask = cpumask_of(cpu);
> clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fff);
>
> - csr_set(sie, SIE_STIE);
> + csr_set(CSR_XIE, XIE_XTIE);
> return 0;
> }
>
> static int riscv_timer_dying_cpu(unsigned int cpu)
> {
> - csr_clear(sie, SIE_STIE);
> + csr_clear(CSR_XIE, XIE_XTIE);
> return 0;
> }
>
> @@ -76,7 +76,7 @@ void riscv_timer_interrupt(void)
> {
> struct clock_event_device *evdev = this_cpu_ptr(_clock_event);
>
> - csr_clear(sie, SIE_STIE);
> + csr_clear(CSR_XIE, XIE_XTIE);
> evdev->event_handler(evdev);
> }
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index c72c036aea76..4ee96ac90ea4 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -179,7 +179,7 @@ static void plic_handle_irq(struct pt_regs *regs)
>
> WARN_ON_ONCE(!handler->present);
>
> - csr_clear(sie, SIE_SEIE);
> + csr_clear(CSR_XIE, XIE_XEIE);
> while ((hwirq = readl(claim))) {
> int irq = irq_find_mapping(plic_irqdomain, hwirq);
>
> @@ -190,7 +190,7 @@ static void plic_handle_irq(struct pt_regs *regs)
> generic_handle_irq(irq);
> writel(hwirq, claim);
> }
> - csr_set(sie, SIE_SEIE);
> + csr_set(CSR_XIE, XIE_XEIE);
> }
>
> /*
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Oct 18, 2019 at 6:19 AM Paul Walmsley wrote:
>
> Resolve most warnings from the 'sparse' static analysis tool for the
> arch/riscv codebase. This makes life easier for us as maintainers,
> and makes it easier for developers to use static analysis tools on
> their own changes.
>
> This
s.S b/arch/riscv/boot/loader.lds.S
> new file mode 100644
> index ..47a5003c2e28
> --- /dev/null
> +++ b/arch/riscv/boot/loader.lds.S
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#include
> +
> +OUTPUT_ARCH(riscv)
> +ENTRY(_start)
> +
> +SECTIONS
> +{
> + . = PAGE_OFFSET;
> +
> + .payload : {
> + *(.payload)
> + . = ALIGN(8);
> + }
> +}
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
/
> csrw CSR_XIE, zero
> csrw CSR_XIP, zero
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
Hi Paul,
On Wed, Oct 16, 2019 at 9:38 PM Anup Patel wrote:
>
> This patch adds riscv_isa bitmap which represents Host ISA features
> common across all Host CPUs. The riscv_isa is not same as elf_hwcap
> because elf_hwcap will only have ISA features relevant for user-space
&g
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git
.
Signed-off-by: Anup Patel
---
arch/riscv/kvm/vcpu.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index f1a218d3a8cf..844542dd13e4 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -662,15
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.txt | 158 +++--
1 file changed, 151 insertions(+), 7 deletions(-)
diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm
(), stage2_unmap_range(), and
stage2_wp_range() helper functions as mentioned above.
Signed-off-by: Anup Patel
---
arch/riscv/kvm/mmu.c | 469 +++
1 file changed, 164 insertions(+), 305 deletions(-)
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index
run-loop.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/kvm_host.h | 3 ---
arch/riscv/kvm/main.c | 6 --
arch/riscv/kvm/vcpu.c | 24 +---
3 files changed, 1 insertion(+), 32 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h
b/a
v0.1 for Guest where CONSOLE_GETCHAR and
CONSOLE_PUTCHART SBI calls are unhandled in KVM RISC-V kernel module
so we forward these calls to userspace. In future when we implement
SBI v0.2 for Guest, we will forward SBI v0.2 experimental and vendor
extension calls to userspace.
Signed-off-by: Anup Patel
---
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 81
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
flush and this will be optimized in future.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_exit.c| 4 ++
arch/riscv
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index f1378c0a447f..7507b859246b
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 25 ++
arch/riscv/kvm/Makefile | 3
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig| 2 +
arch
-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58
.
One of the use-case for riscv_isa bitmap is in KVM hypervisor where
we will use it to do following operations:
1. Check whether hypervisor extension is available
2. Find ISA features that need to be virtualized (e.g. floating
point support, vector extension, etc.)
Signed-off-by: Anup Patel
REG interface for CSR access to user-space
- Removed irqs_pending_lock and use atomic bitops instead
- Added separate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (18):
RISC-V: Add bitmap reprensenting ISA features common across CPUs
RISC-V: A
)
>
> +#define FIXADDR_TOP (VMEMMAP_START)
> +#ifdef CONFIG_64BIT
> +#define FIXADDR_SIZE PMD_SIZE
> +#else
> +#define FIXADDR_SIZE PGDIR_SIZE
> +#endif
> +#define FIXADDR_START(FIXADDR_TOP - FIXADDR_SIZE)
> +
> /*
> * ZERO_PAGE is a global shared page that is always zero,
> * used for zero-mapped memory areas, etc.
> --
> 2.17.1
>
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> -Original Message-
> From: Palmer Dabbelt
> Sent: Saturday, October 12, 2019 11:09 PM
> To: Anup Patel
> Cc: Paul Walmsley ; a...@eecs.berkeley.edu;
> Greg KH ; r...@google.com; Atish Patra
> ; Alistair Francis ;
> Christoph Hellwig ; a...@bra
On Wed, Oct 9, 2019 at 4:14 AM Palmer Dabbelt wrote:
>
> On Mon, 23 Sep 2019 04:12:17 PDT (-0700), pbonz...@redhat.com wrote:
> > On 04/09/19 18:15, Anup Patel wrote:
> >> +unsigned long guest_sstatus =
> >> +vcpu->arch.guest_context.sst
On Sat, Sep 28, 2019 at 3:51 AM Christoph Hellwig wrote:
>
> On Thu, Sep 26, 2019 at 05:09:15PM -0700, Atish Patra wrote:
> > All SBI related macros can be reused by KVM RISC-V and userspace tools
> > such as kvmtool, qemu-kvm. SBI calls can also be emulated by userspace
> > if required. Any
On Fri, Sep 27, 2019 at 5:39 AM Atish Patra wrote:
>
> The SBI v0.2 introduces a base extension which is backward compatible
> with v0.1. Implement all helper functions and minimum required SBI
> calls from v0.2 for now. All other base extension function will be
> added later as per need.
> As
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git
v0.1 for Guest where CONSOLE_GETCHAR and
CONSOLE_PUTCHART SBI calls are unhandled in KVM RISC-V kernel module
so we forward these calls to userspace. In future when we implement
SBI v0.2 for Guest, we will forward SBI v0.2 experimental and vendor
extension calls to userspace.
Signed-off-by: Anup Patel
---
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.txt | 158 +++--
1 file changed, 151 insertions(+), 7 deletions(-)
diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
The following features are not supported yet and will be added in
future:
1. A time offset to adjust guest time from host time
2. A saved next event in guest vcpu for vm migration
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
This patch implements all required functions for programming
the stage2 page table for each Guest/VM.
At high-level, the flow of stage2 related functions is similar
from KVM ARM/ARM64 implementation but the stage2 page table
format is quite different for KVM RISC-V.
Signed-off-by: Anup Patel
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 25 ++
arch/riscv/kvm/Makefile | 3
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 81
flush and this will be optimized in future.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 2 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_exit.c| 4 ++
arch/riscv
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked
will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 9 +-
arch/riscv/kernel/asm-offsets.c | 76
arch/riscv/kvm/Makefile | 2
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index f1378c0a447f..7507b859246b
.
One of the use-case for riscv_isa bitmap is in KVM hypervisor where
we will use it to do following operations:
1. Check whether hypervisor extension is available
2. Find ISA features that need to be virtualized (e.g. floating
point support, vector extension, etc.)
Signed-off-by: Anup Patel
401 - 500 of 2147 matches
Mail list logo
