2. aridity --> arity

~PM

> From: [email protected]
> To: [email protected]
> Date: Tue, 12 Aug 2014 10:46:08 -0500
> Subject: [agi] New Post-Doctoral Researcher Joining the Effort...
> 
> Greetings all…
> 
> This is my post on the first milestone I promised in my previously posted 
> introduction.  Attached is my research description for the 
> Emulator-Translator [E-T] framework.  This framework is based on my doctorial 
> disssertation I finished in Octorber 2011 (see 
> http://gradworks.umi.com/34/81/3481012.html ).
> 
> The E-T framework prescribes a methodology for translating a functional 
> abstract AGI model into a prototype Mind OS [operating system].  The abstract 
> AGI model will be developed on a Java platform that utilizes OpenCog, on a 
> C++/Linux platform, as a local server.  This model is used to test and 
> develop another abstract model that is closer to a hardware implementation 
> using DSP Robotics FlowStone programming paradigm.  This model is used to 
> develop the physical hardware architecture that becomes realized as a 
> prototype Mind OS on the implementation platform.
> 
> Note that this research and development has a dependency on and uses the 
> ongoing development for OpenCog Prime.  This research does not seek to 
> ‘reinvent the wheel’, but works with those colleagues that are developing 
> OpenCog.
> 
> This research and development will make the following novel contributions to 
> the Novamente approach to AGI:
> 
> 1.  One atom architecture for all memory types {episodic, etc...}.
> 
> 2.  Both Link and Node atoms can have multiple aridity when linking with 
> other atoms.
> 
> 3.  The use of the atom as the elemental building block for atom spaces that 
> function as
>       knowledge bases separate from the Mind Agents that perform cognitive 
> tasks.
> 
> 4.  This knowledge base architecture will attempt to implement built-in PLN 
> and hBOA.
> 
> The end result of this design science research and development will be a 
> primitive prototype of a Mind OS, illustrated in the research description, 
> incorporating two parallel processing chips and three FPGA chips.
> 
> Again, I welcome your comments, questions, ideas, evaluations, and 
> constructive criticism on this post.  Again, go easy on me, for I am a 
> newbie.  Also, let me know if I am unwittingly ‘reinventing the wheel’ that 
> would be someone elses work.
> 
> Until next post…
> 
> Daniel Martin, Ph.D.
> 
> 
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