DCtoDaylight;324918 Wrote: > I'm afraid you don't understand what jitter is... > Jitter is variation on the timing of one sample to the next. You can't > remap jitter, it has no effect on the data (unless it's so grossly large > that it causes read errors, not the case here). > > Most sample rate conversions, particularly ones that move from 44.1k to > 48/96/192k are fully asynchronous. As a result, they totally remove > incoming jitter, because the incoming clock is not used at all in > clocking the output data. If the DAC1 does this sort of SRC, and > doesn't block incoming jitter, then someone messed when designing it. > > > Dave
But with asychcronous reclocking you certainly embed it from the analog domain of jitter within the digital signal. Simply consider a asychronous reclocking from nominal 44.1kHz to the same 44.1kHz. Unless both the input clock and reclocking are jitter free as well as exactly the same frequency, the result is not going to be bit perfect, nor is it going to be and exact shift of a perfectly interpolated signal. As to whether this distortion is discernable, dunno, but that is not answerable by hand waving.... in other words, what Patrick said above. FWIW -- occam ------------------------------------------------------------------------ occam's Profile: http://forums.slimdevices.com/member.php?userid=949 View this thread: http://forums.slimdevices.com/showthread.php?t=50147 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
