DCtoDaylight;325102 Wrote: > ...Again, an asynchronous interface will only use the received clock for > receiving the data. It's jitter is of no concern, and will never harm > the output...
DC, if you are willing, please feel free to educate me here. :) My questions: If the digital datastream is mis-timed upon receipt due to sending-clock and/or transmission-interface jitter, this mis-timed data will of course be received as such at the next device, and merely be re-encoded by the SRC. The data will be intact, but the timing of the data will not. So, how can simply remapping mis-timed data into a higher sample-rate, possibly "eliminate" any of the originally received jitter artifacts? I understand that this process (after remapping) will allow the data to be internally sent to the DAC chip with little/no secondary internal jitter, and the DAC chip will then do its part accordingly - but surely the original received jitter artifacts will still be there, just perhaps changed in their audible characteristics? Again, please feel free to correct me here, as I will gratefully receive it. -- NewBuyer ------------------------------------------------------------------------ NewBuyer's Profile: http://forums.slimdevices.com/member.php?userid=7862 View this thread: http://forums.slimdevices.com/showthread.php?t=50147 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
