Re: [casper] Casper 10.1 library issue

[Henry Chen]

Hi Wanxiang,

The different FFTs are documented at

http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node24.html
http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node25.html
http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node26.html
http://casper.berkeley.edu/doc/mlib_devel_7_1/doc/html/node27.html

But in summary the base FFT block handles complex inputs and gives
complex outputs, and is completely parameterized to configure itself
for biplex (2 independent channel inputs) or wideband (single channel,
demultiplexed inputs). The real FFT takes real inputs and gives complex
outputs, discarding the complex conjugates.

For information about the sync input, please see the memo at

http://casper.berkeley.edu/memos/sync_memo_v1.pdf

Thanks,
Henry

wan.ch...@csiro.au wrote:

HI Andrew:

Thank you for your answer. Now I have better idea on how the libraries are organized. What I am do is to setup the simulink simulation. Do you know the difference among several FFT module provided in the casper library? They are : fft_biplex_real_2x

fft_biplex_real_4x
fft
fft_wideband_real

And by the way, what are the function for the shift and sync pin? Thanks Wan

------------------------------------------------------------------------
*From:* Andrew Martens [mailto:martens.and...@gmail.com]
*Sent:* Thursday, 30 October 2008 6:11 PM
*To:* Cheng, Wan (ATNF, Marsfield)
*Cc:* laura.spit...@gmail.com; casper@lists.berkeley.edu
*Subject:* Re: [casper] Casper 10.1 library issue

Hi Wan

Matlab scripts generate and modify an EDK project containing the HDL code for the ADC. gen_xps_files.m (in xps_library directory) does most of the work (look from line 246 or so) of copying a base EDK project (in xps_lib directory) and then modifying it based on what your Simulink design contains. There are different base EDK projects for each hardware platform. The base EDK project contains the HDL relevant to the ADC (in pcores/adc_interface_*) and the Matlab script modifes other files (system.mhs, system.mss, data/system.ucf etc) to ensure the ADC related infrastructure is included in the final EDK project. This is not a very simple process and I am not sure where you want to jump in.

Regards
Andrew

2008/10/30 <wan.ch...@csiro.au>

    HI Laura:

Thanks for your help. You are right. If I set more samples per

    period, it is more difficult for me to find the difference. I setup
    the sine wave according your setting, the difference is obvious.

I think you explanation for the ADC internal structure is correct.

    The extra delay in O1 is for alignment. But I still have one more
    question:

How the ADC module is linked to the HDL code in the library? Some

    low level function, such as convert the DDR data into single sample
    edge data, rebuffer the ADC clock, is done by HDL code. But I can
    not see how these HDL files are included into the design flow. Do
    you have any idea?

Thanks Wan

    ------------------------------------------------------------------------
    *From:* Laura Spitler [mailto:laura.spit...@gmail.com
    <mailto:laura.spit...@gmail.com>]
    *Sent:* Thursday, 30 October 2008 1:48 AM

    *To:* Cheng, Wan (ATNF, Marsfield)
    *Cc:* casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>
    *Subject:* Re: [casper] Casper 10.1 library issue

    Hi Wan,

    That is strange. I made a model that looks identical to your AC_test
    using 10.1, and the output looks correct.
    Here are the parameters I'm using for the 'Sine Wave' block:
    Sine type : Sample based
    Amplitude: 1
    Bias: 0
    Samples per period: 10
    Number of offset samples: 0
    Sample time: 1/8

    The sample time of the ADC block should be 1.

    The ADC block uses 4 or 8 downsample blocks for interleave off and
    on respectively to mimic the parallel output of the ADC, which is
    why you have to set sample time to either 1/4 or 1/8. The line with
    the delay block set to 2 rather than 1 is connected to the
    downsample block with offset sample = 0. My guess is the latency
    through the downsample block for the o0 sample is zero, so to keep
    it aligned with o1-o7, it needs an extra delay. If I'm wrong,
    someone correct me. In any case I don't think this is your trouble.

    If you're still having trouble, feel free to email me your model and
    I'll take a look at it.

    Good luck,
    Laura

    On Tue, Oct 28, 2008 at 10:37 PM, <wan.ch...@csiro.au> wrote:

        Hi Laura:

When I set the sample time of sine wave to 1/8, all outputs are

        still same. I look at the subsystem of ADC module, and I find,
        except O1 has 1 more cycle delay, all other channel have same
        function. I am not sure how the ADC is implement. Do you have
        any idea?

Thanks Wan

        ------------------------------------------------------------------------
        *From:* Laura Spitler [mailto:laura.spit...@gmail.com
        <mailto:laura.spit...@gmail.com>]
        *Sent:* Wednesday, 29 October 2008 12:15 PM
        *To:* Cheng, Wan (ATNF, Marsfield)
        *Cc:* casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>
        *Subject:* Re: [casper] Casper 10.1 library issue

        Hi Wan,
        In the Simulink 'Sine Wave' block, do you have your sample time
        set to 1/8 or 1? Similarly if you turn interleave off, the
        sample time should be 1/4.

        Best,
        Laura


        On Tue, Oct 28, 2008 at 8:59 PM, <wan.ch...@csiro.au> wrote:

            Hi All:

I just set a simple ADC module in simulink and check the ADC

            output. But the issue is that all eight outputs have same
            output data. This is different with showed in manual. From
            manual, these output should generate 8 sequence sampling.
            But as I know, they seems same. For details, please see the
            attached.

Any idea? Thanks Wan