Hi, Randy, On Mar 4, 2010, at 11:06 , Randy Mccullough wrote:
Is it possible, using the four SYNC outputs of the ADC block, to ascertain which of the 8 samples presented during a logic clock cycle was most closely aligned with an in-coming 1PPS signal?
Even if the ADC sampling is synchronous with the 1 PPS signal, I think there is a 0/90/180/270 degree phase ambiguity between the Fs/4 ADC output clock and the 1 PPS signal, so I don't think you can be guaranteed that a given sync output corresponds to a given ADC output from power cycle to power cycle. While the board is running however, our experience at the ATA has shown that things are stable in whichever one of the four possible states it happened to come up in.
At the ATA, an internal 1 PPS is generated from the FPGA clock (which is a divided down version of the ADC sample clock). This internal 1 PPS is sync'ed to the external 1 PPS at power on (or via software "rearm"). The fixed delays are calibrated in the system (including the ADC sample "delay" ambiguity) whenever power is cycled (or the ibobs otherwise reinitialized), but that turns out to be fairly infrequently so it's not too burdensome.
Hope this helps, Dave
