Hi Dave,
You can't tell which of the 4 clock traces you get into the FPGA. But
whichever phase you get becomes your reference into the DCM, which
generates the 0/90/180/270 phase lines for the lower speed clock.
Data will be aligned with one of the 0/90/180/270 phases (can't
remember which) after going through DDR registers. Since those are
the same clocks used to sample the sync line, there should be no
ambiguity if the delays are properly matched.
-Suraj
On Mar 4, 2010, at 4:03 PM, David MacMahon wrote:
Hi, Dan,
On Mar 4, 2010, at 15:15 , Dan Werthimer wrote:
i don't think there will be a power up divide by four ambiguity if
you only have
one adc board
I think there will be a divide by four ambiguity even for one ADC
board. Assuming the ADC sample clock is synchronous to 1 PPS, there
is no way to tell (without somehow calibrating) which of the four
ADC CLK OUT signals the FPGA will get as its input clock.
For this input...
1 PPS 000001111111111111111...
ADC CLK IN 010101010101010101010...
You will get one of these outputs...
ADC CLK OUT 100001111000011110000...
ADC CLK OUT 111000011110000111100...
ADC CLK OUT 011110000111100001111...
ADC CLK OUT 000111100001111000011...
...but how can you tell which one you've got?
Dave
