The idea is to use the sync pulse to phase up ADCs across multiple
host boards. For this, it does work as expected and Suraj is correct
in his explanation (within one jitter clock as Dan's outlined). Delay
correction is not implemented, so while the 1PPS can be used for phase
corrections, it's no good to calibrate absolute delay. This means it's
useless to Paul (unless he calibrates it manually) but works fine for
syncing ADCs to within one sample clock across multiple boards (as in
correlator application) where we want all ADCs to be phased the same,
but don't care about absolute delay of the signal. This works because
the delay (routing) is the same across all ADC boards and ZDOK
interfaces. As I outlined earlier though, it doesn't work when there
are two ADCs per FPGA though.
Jason
On 04 Mar 2010, at 17:17, David MacMahon wrote:
Hi, Suraj,
On Mar 4, 2010, at 16:27 , Suraj Gowda wrote:
You can't tell which of the 4 clock traces you get into the FPGA.
But whichever phase you get becomes your reference into the DCM,
which generates the 0/90/180/270 phase lines for the lower speed
clock. Data will be aligned with one of the 0/90/180/270 phases
(can't remember which) after going through DDR registers. Since
those are the same clocks used to sample the sync line, there
should be no ambiguity if the delays are properly matched.
This is an interesting point I had not considered, but it seems to
rely on a level of synchronization/coherency between 1 PPS and the
sample clock that could be hard to guarantee/maintain. It might be
easier to implement something utilizing this idea in the underlying
VHDL code where one has access to the different clock phase
domains. By the time the four sync signals get into Simulink
they're all in the same clock phase domain. And it still doesn't
obviate the need to calibrate (since that need is basically
intrinsic to any precise measurement) so why bother?
Dave
