On Thu, Mar 4, 2010 at 4:49 PM, Dan Werthimer <[email protected]> wrote: > > > hi jason, dave and paul, > > regarding syncing up one or two adc's with 1 PPS: > > at boot up, the iADC (also called ADC2x1000-8), > yellow block software/gateware aligns two adc's that are plugged into roach > or ibob. > the code does this by sampling the relative phase of the two clocks that > emerge from each adc > (these clocks are generated internally in each adc, by dividing the > sample clock by four); the code resets one of the adc's until > the two adc clocks are lined up in phase. > > although it might be possible to crudely recover the phase of the 1PPS > signal > by looking at all four sync pulses, in practice, as you guys point out, > it's better to calibrate this delay, best by looking at a known source on > the sky, > or possibly digitizing the 1 PPS by coupling it into the analog input and > then finding > it's edge in software using lots of samples. > this is should be done everytime the system is powered up.
I'm still a little confused, and I'll be dealing with this in the not-terribly-far future as well. Is the issue that the ADCs each divide their clock by 4 separately and those two clocks may have different phases? If so, isn't one of them (the one that the FPGA gets its clock from) always in phase with the FPGA by definition? If so, why not just inject the sync signal into the same ADC? (And if you've aligned the clocks of the two ADCs on startup, why is there any uncertainty at all, even on the other ADC?) --Andy
