Yes, I think a parameter is a good idea. Maybe just a radio-box or a
drop-down-selection in the mask. Multiple cores will confuse users
(like everyone gets confused by the multiple FFT blocks) and will
probably become an admin nightmare down the road.
Jason
On 23 Apr 2010, at 07:40, Dan Werthimer wrote:
hi jason,
perhaps we can have different yellow block cores,
one hardened for people that need high speed input,
one not hardened,
or better yet - a parameter that selects whether the
routing is hardened or not?
dan
On 4/22/2010 10:32 PM, Jason Manley wrote:
suraj is planning on hardening the yellow block cores
so that their routing/timing is locked down, independent
of what else is running in the fpga.
Please don't make this the default behaviour. On designs that are
nearly fully packed (99%), you need to be able to twiddle every
part of the design to make it fit, and sometimes that means re-
arranging the yellow blocks' innards. Part of the BEE2 DRAM
controller was hard-routed and it caused complications when the
chip got full.
Jason
On 4/22/2010 2:57 PM, Mark Wagner wrote:
Hi John,
I don't think anyone has been able to get a spectrometer working
at the full 3GS/s interleaved yet. The best Suraj and I have
been able to do is about 2.4Gs/s before we start running into
serious timing issues. We do have plans to meet soon with a
Xilinx timing expert in the hopes of resolving our issues.
Mark
On Thu, Apr 22, 2010 at 2:12 PM, John Ford <[email protected]> wrote:
Hi all.
Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s
ADC
boards on a ROACH? I seem to recall someone doing something of
the sort,
but I don't recall any details.
Thanks for any info!
John
