Hi Nimish We have been making a lot of changes to the ROACH2 infrastructure in the last few weeks. This includes fixes that improve timing scores considerably (software registers were being connected so that the FPGA clock was registering the value instead of the EPB clock and the EPB clock domain timing constraint was set to 88 MHz when we only use it at 66.6MHz). These fixes should help you a lot. I will push these changes to our github repository this morning.
I will look at adding an option to the yellow block to allow the user to choose the optimisation without having to break the library links. Regards Andrew On Mon, 2012-03-05 at 15:38 -0500, Nimish Sane wrote: > Hi all, > > > We are using multiple "shared bram" yellow blocks in our FX correlator > design (ska-sa software library, Xilinx 11.4 tools, Linux, Roach 2, > KatADC, 150MHz FPGA clock — eventually 300 MHz). We want to store > some gain/scaling and other coefficients in this memory and read from > the memory during run-time. These blocks utilize around 50% of BRAM > resources on Roach 2. I cannot get rid of timing errors with the > shared bram blocks. I have tried various configurations of shared bram > blocks. The closest I have got is when I broke the library link of > these yellow blocks and changed bram implementation to optimize speed > instead of area. Still, few (3) small timing errors persist. > > > Are there any specific things to keep in mind while using this block? > Does anyone have any experience or suggestions to share? > > > Thanks, > > > Nimish
