Hi all, We are using multiple "shared bram" yellow blocks in our FX correlator design (ska-sa software library, Xilinx 11.4 tools, Linux, Roach 2, KatADC, 150MHz FPGA clock — eventually 300 MHz). We want to store some gain/scaling and other coefficients in this memory and read from the memory during run-time. These blocks utilize around 50% of BRAM resources on Roach 2. I cannot get rid of timing errors with the shared bram blocks. I have tried various configurations of shared bram blocks. The closest I have got is when I broke the library link of these yellow blocks and changed bram implementation to optimize speed instead of area. Still, few (3) small timing errors persist.
Are there any specific things to keep in mind while using this block? Does anyone have any experience or suggestions to share? Thanks, Nimish
