Hi Nimish The changes only affect the software registers but the result is that the whole design makes timing a lot easier, including shared bram blocks.
There are a couple of things that the commits affect though; - you will need to replace software register yellow blocks from the library for existing designs. - you will need to replace ten_Gbe_v2 yellow blocks from the library for existing designs. Regards Andrew On Tue, 2012-03-06 at 11:18 -0500, Nimish Sane wrote: > Thanks Andrew! I will try out and let you know. > > > Do these changes affect software registers alone or other blocks as > well — in particular, the shared bram block? > > > Thanks, > > > Nimish > > On Tue, Mar 6, 2012 at 10:17 AM, Andrew Martens <[email protected]> > wrote: > Hi Nimish > > commit 3282865 just pushed to ska-sa github repo. ROACH2 > related changes > should fix your timing issues. > > Let us know if you have any problems. > > Regards > Andrew > > On Mon, 2012-03-05 at 15:38 -0500, Nimish Sane wrote: > > > Hi all, > > > > > > We are using multiple "shared bram" yellow blocks in our FX > correlator > > design (ska-sa software library, Xilinx 11.4 tools, Linux, > Roach 2, > > KatADC, 150MHz FPGA clock — eventually 300 MHz). We want to > store > > some gain/scaling and other coefficients in this memory and > read from > > the memory during run-time. These blocks utilize around 50% > of BRAM > > resources on Roach 2. I cannot get rid of timing errors with > the > > shared bram blocks. I have tried various configurations of > shared bram > > blocks. The closest I have got is when I broke the library > link of > > these yellow blocks and changed bram implementation to > optimize speed > > instead of area. Still, few (3) small timing errors persist. > > > > > > Are there any specific things to keep in mind while using > this block? > > Does anyone have any experience or suggestions to share? > > > > > > Thanks, > > > > > > Nimish > > > > >
