Hi Glen.
We've also been experimenting with adding TIG (timing ignore) statements to > the timing constraint file so that things like shared registers are not > constrained to meet timing, since it shouldn't make much difference. This > is not yet commonly done though. > > I would be very nervous about disabling timing checks in general. Metastability will bite you in weird and unexpected ways. For example you may have a control word stored in a BRAM (or software register) that may present itself as an unintended/intermediate/oscillating value for an indefinite period of time (although often with a small probability). It is standard practice to register multiple times and have an arbiter when asynchronous logic is involved. I would venture to guess that the overhead of fixing the timing error would be less than this additional logic. So I guess I'm saying: fix the timing error and don't disable the timing checks. Remember the R2 chip is massive, four times the area. It makes sense that more register stages are needed in and out of peripherals that worked for R1. I guess it is easy to say from someone not doing the work ;) Good luck. Cheers, David
