I have a simple design which implements an A/D conversion on port A1 of the ADC16 board and maps the ADC output as follows:
LED 0 <= A1[4] LED 1 <= not A1[4] LED 2 <= A1[5] LED 3 <= not A1[5] LED 4 <= A1[6] LED 5 <= not A1[6] LED 6 <= A1[7] LED 7 <= '1' when the clock 'sys_clk' is selected with a rate of 150MHz, LED 7, LED 5, LED 3, and LED 1 lit while the rest of the LEDs are not lit. This is the expected behavior if the ADCs are not capturing data (A1 is stuck at zero). when the clock 'adc0_clk' is selected with a rate of 150MHz and a 150MHz sine at 3 dbm is presented to the ADC clock input of the Roach 2 board, none of the LEDs are lit. This behavior seems to be consistent with the xilinx chip not receiving a clocking input. Can someone provide a clue as to how to fix this problem? Thanks, -Joe Kujawski
