Hi Joe
When you try with adc0_clk at 150MHz does LED 7 light up? This LED
should be independent of the clock source.
If it is not lit it indicates that the FPGA may not have been configured
or has not come up properly. You may want to try writing to and then
reading from the register 'sys_scratchpad'. This is included in every
bof file and can be used to help check that the FPGA has been configured
correctly.
You could also connect an LED to the most significant bit of a large
counter (27 bits or so). This would make the LED independent of the
actual ADC data and just depend on a valid clock (a snapshot block could
be used to capture raw data from the ADC to check ADC performance).
Cheers
Andrew
I have a simple design which implements an A/D conversion on port A1
of the ADC16 board and maps the ADC output as follows:
LED 0 <= A1[4]
LED 1 <= not A1[4]
LED 2 <= A1[5]
LED 3 <= not A1[5]
LED 4 <= A1[6]
LED 5 <= not A1[6]
LED 6 <= A1[7]
LED 7 <= '1'
when the clock 'sys_clk' is selected with a rate of 150MHz, LED 7, LED
5, LED 3, and LED 1 lit while the rest of the LEDs are not lit. This
is the expected behavior if the ADCs are not capturing data (A1 is
stuck at zero).
when the clock 'adc0_clk' is selected with a rate of 150MHz and a
150MHz sine at 3 dbm is presented to the ADC clock input of the Roach
2 board, none of the LEDs are lit. This behavior seems to be
consistent with the xilinx chip not receiving a clocking input.
Can someone provide a clue as to how to fix this problem?
Thanks,
-Joe Kujawski
