Dave, --You said to execute the following line:
gem update --source http://astro.berkeley.edu/~davidm/gems adc16 --Response on my (non-Roach, Windows computer) is: Updating installed gems Nothing to update -- You said that I can execute the following line of code and also that it need not be executed on the ROACH2 board (2 separate emails). Once I get to this point, is this the exact line that I will need to execute on a non-ROACH, Windows computer? $ adc16_init.rb pf1 roach2_fengine.bof -Joe Kujawski On Wed, Oct 9, 2013 at 2:12 AM, David MacMahon <[email protected]>wrote: > Hi, Joe, > > The ADCs on the ADC16 board are somewhat different from other ADCs used on > other CASPER ADC boards. The ADC chips on the ADC16x250-8 board do not > fully power up when power is applied. They need to be turned on via > software and then the FPGA input delay blocks need to be calibrated to > account for the design-specific clock skew at the FPGA SERDES inputs and to > properly frame the de-serialized bytes. > > Here is a high level overview of the startup sequence: > > Program FPGA with ADC16 design > Turn on ADC chips via software > Re-program FPGA with same design > Calibrate input delays > Bitslip SERDES blocks until data if properly framed > > There is software already written to do this. It is written in Ruby. You > need to have Ruby (1.9 or later recommended) and Rubygems installed. You > can then install the ADC16 software with: > > gem update --source http://astro.berkeley.edu/~davidm/gems adc16 > > This will give you a command "adc16_init.rb" that you can use to program > the FPGA and perform all the calibration steps required. Here is a sample > command line session using adc16_init.rb: > > $ adc16_init.rb pf1 roach2_fengine.bof > Connecting to pf1... > Programming pf1 with roach2_fengine.bof... > Design built for ROACH2 rev2 with 8 ADCs (ZDOK rev2) > Resetting ADC, power cycling ADC, and reprogramming FPGA... > ZDOK0 clock OK, ZDOK1 clock OK > Calibrating SERDES blocks...ABCDEFGH > SERDES calibration successful. > Selecting analog inputs... > Done! > > The adc16_init.rb script expects/requires the bof file to be in the > tcpborphserver's boffiles directory (i.e. already on the ROACH2 > filesystem). The adc16_init.rb script does NOT support dynamically > uploading the BOF via the "?uploadbof" command. > > Hope this helps, > Dave > > On Oct 8, 2013, at 3:38 PM, Kujawski, Joseph wrote: > > > I have a simple design which implements an A/D conversion on port A1 of > the ADC16 board and maps the ADC output as follows: > > > > LED 0 <= A1[4] > > LED 1 <= not A1[4] > > LED 2 <= A1[5] > > LED 3 <= not A1[5] > > LED 4 <= A1[6] > > LED 5 <= not A1[6] > > LED 6 <= A1[7] > > LED 7 <= '1' > > > > when the clock 'sys_clk' is selected with a rate of 150MHz, LED 7, LED > 5, LED 3, and LED 1 lit while the rest of the LEDs are not lit. This is > the expected behavior if the ADCs are not capturing data (A1 is stuck at > zero). > > > > when the clock 'adc0_clk' is selected with a rate of 150MHz and a 150MHz > sine at 3 dbm is presented to the ADC clock input of the Roach 2 board, > none of the LEDs are lit. This behavior seems to be consistent with the > xilinx chip not receiving a clocking input. > > > > Can someone provide a clue as to how to fix this problem? > > > > Thanks, > > > > -Joe Kujawski > > > > -- ************************************** * Joe Kujawski * Siena College * Dept. of Physics and Astronomy, RB 113 * 515 Loudon Road * Loudonville, NY 12211-1462 * * Email: [email protected] * Phone: 518-782-6885 * Fax: 518-783-2986 **************************************
